GD32F130 1.0 GD32F1x0 ARM 32-bit Cortex-M3 Microcontroller based device CM3 r2p1 little 0 0 4 0 8 32 0x20 0x0 0xFFFFFFFF ADC Analog to digital converter ADC 0x40012400 0x0 0x400 registers ADC_CMP 12 STAT STAT status register 0x0 0x20 read-write 0x00000000 STRC Start flag of regular channel group 4 1 STRCRreadNotStartedNo regular channel conversion started0StartedRegular channel conversion has started1 STRCWwriteClearClear the regular channel start flag0 STIC Start flag of inserted channel group 3 1 STICRreadNotStartedNo inserted channel group conversion started0StartedInserted channel group conversion has started1 STICWwriteClearClear the inserted channel group start flag0 EOIC End of inserted group conversion flag 2 1 EOICRreadNotCompleteConversion is not complete0CompleteConversion complete1 EOICWwriteClearClear end of inserted group conversion flag0 EOC End of group conversion flag 1 1 EOCRreadNotCompleteConversion is not complete0CompleteConversion complete1 EOCWwriteClearClear end of group conversion flag0 WDE Analog watchdog event flag 0 1 WDERreadNoEventNo analog watchdog event occurred0EventAnalog watchdog event occurred1 WDEWwriteClearClear the analog watchdog event flag0 CTL0 CTL0 control register 0 0x4 0x20 read-write 0x00000000 RWDEN Regular channel analog watchdog enable 23 1 RWDENread-writeDisabledAnalog watchdog disabled on regular channels0EnabledAnalog watchdog enabled on regular channels1 IWDEN Inserted channel analog watchdog enable 22 1 IWDENread-writeDisabledAnalog watchdog disabled on inserted channels0EnabledAnalog watchdog enabled on inserted channels1 DISNUM Number of conversions in discontinuous mode 13 3 07 DISIC Discontinuous mode on injected channels 12 1 DISICread-writeDisabledDiscontinuous mode on inserted channels disabled0EnabledDiscontinuous mode on inserted channels enabled1 DISRC Discontinuous mode on regular channels 11 1 DISRCread-writeDisabledDiscontinuous mode on regular channels disabled0EnabledDiscontinuous mode on regular channels enabled1 ICA Inserted channel group convert automatically 10 1 ICAread-writeDisabledAutomatic inserted group conversion disabled0EnabledAutomatic inserted group conversion enabled1 WDSC When in scan mode, analog watchdog is effective on a single channel 9 1 WDSCread-writeAllAnalog watchdog enabled on all channels0SingleAnalog watchdog enabled on a single channel1 SM Scan mode 8 1 SMread-writeDisabledScan mode disabled0EnabledScan mode enabled1 EOICIE Interrupt enable for EOIC 7 1 EOICIEread-writeDisabledEOIC interrupt disabled0EnabledEOIC interrupt enabled. An interrupt is generated when the EOIC bit is set1 WDEIE Interrupt enable for WDE 6 1 WDEIEread-writeDisabledWDE interrupt disabled0EnabledWDE interrupt enabled. An interrupt is generated when the WDE bit is set1 EOCIE Interrupt enable for EOC 5 1 EOCIEread-writeDisabledEOC interrupt disabled0EnabledEOC interrupt enabled. An interrupt is generated when the EOC bit is set1 WDCHSEL Analog watchdog channel select 0 5 018 CTL1 CTL1 control register 1 0x08 0x20 read-write 0x00000000 VBATEN enable/disable the VBAT channel 24 1 VBATENread-writeDisabledVBAT channel disabled0EnabledVBAT channel enabled1 TSVREN Channel 16 and 17 enable of ADC 23 1 TSVRENread-writeDisabledChannel 16 and 17 disabled0EnabledChannel 16 and 17 enabled1 SWRCST Start on regular channel 22 1 SWRCSTRreadStartedReset state0NotStartedStarting conversion of regular channels1 SWRCSTWwriteStartStart conversion of regular channels1 SWICST Start on inserted channel 21 1 SWICSTRreadStartedReset state0NotStartedStarting conversion of inserted channels1 SWICSTWwriteStartStart conversion of inserted channels1 ETERC External trigger enable for regular channel 20 1 ETERCread-writeDisabledConversion on external event disabled0EnabledConversion on external event enabled1 ETSRC External trigger select for regular channel 17 3 ETSRCread-writeTimer0Ch0Timer 0 channel 0 event0Timer0Ch1Timer 0 channel 1 event1Timer0Ch2Timer 0 channel 2 event2Timer1Ch1Timer 1 channel 1 event3Timer2TrgoTimer 2 TRGO event4Timer14Ch0Timer 14 channel 0 event5Exti11EXTI line 116SwrcstSWRCST7 ETEIC External trigger enable for inserted channel 15 1 ETEICread-writeDisabledConversion on external event disabled0EnabledConversion on external event enabled1 ETSIC External trigger select for inserted channel 12 3 ETSICread-writeTimer0TrgoTimer 0 TRGO event0Timer0Ch3Timer 0 channel 3 event1Timer1TrgoTimer 1 TRGO event2Timer1Ch0Timer 1 channel 0 event3Timer2Ch2Timer 2 channel 3 event4Timer14TrgoTimer 14 TRGO event5Exti15EXTI line 156SwicstSWICST7 DAL Data alignment 11 1 DALread-writeRightRight alignment0LeftLeft alignment1 DMA DMA request enable 8 1 DMAread-writeDisabledDMA mode disabled0EnabledDMA mode enabled1 RSTCLB Reset calibration 3 1 RSTCLBRreadCompleteCalibration completed0NotCompleteCalibrating1 RSTCLBWwriteStartEnable calibration1 CLB ADC calibration 2 1 CLBRreadCompleteCalibration completed0NotCompleteCalibrating1 CLBWwriteStartEnable calibration1 CTN Continuous mode 1 1 CTNread-writeSingleSingle conversion mode0ContinuousContinuous conversion mode1 ADCON ADC ON 0 1 ADCONread-writeDisabledDisable ADC conversion/calibration and go to power down mode0EnabledEnable ADC and to start conversion1 SAMPT0 SAMPT0 Sampling time register 1 0x0C 0x20 read-write 0x00000000 SPT10 Channel 10 sample time selection 0 3 SPT10read-writeCycles1_51.5 ADC clock cycles0Cycles7_57.5 ADC clock cycles1Cycles13_513.5 ADC clock cycles2Cycles28_528.5 ADC clock cycles3Cycles41_541.5 ADC clock cycles4Cycles55_555.5 ADC clock cycles5Cycles71_571.5 ADC clock cycles6Cycles239_5239.5 ADC clock cycles7 SPT11 Channel 11 sample time selection 3 3 SPT12 Channel 12 sample time selection 6 3 SPT13 Channel 13 sample time selection 9 3 SPT14 Channel 14 sample time selection 12 3 SPT15 Channel 15 sample time selection 15 3 SPT16 Channel 16 sample time selection 18 3 SPT17 Channel 17 sample time selection 21 3 SPT18 Channel 18 sample time selection 24 3 SAMPT1 SAMPT1 Sampling time register 2 0x10 0x20 read-write 0x00000000 SPT0 Channel 0 sample time selection 0 3 SPT0read-writeCycles1_51.5 ADC clock cycles0Cycles7_57.5 ADC clock cycles1Cycles13_513.5 ADC clock cycles2Cycles28_528.5 ADC clock cycles3Cycles41_541.5 ADC clock cycles4Cycles55_555.5 ADC clock cycles5Cycles71_571.5 ADC clock cycles6Cycles239_5239.5 ADC clock cycles7 SPT1 Channel 1 sample time selection 3 3 SPT2 Channel 2 sample time selection 6 3 SPT3 Channel 3 sample time selection 9 3 SPT4 Channel 4 sample time selection 12 3 SPT5 Channel 5 sample time selection 15 3 SPT6 Channel 6 sample time selection 18 3 SPT7 Channel 7 sample time selection 21 3 SPT8 Channel 8 sample time selection 24 3 SPT9 Channel 9 sample time selection 27 3 IOFF0 IOFF0 Inserted channel data offset register 0 0x14 0x20 read-write 0x00000000 IOFF Data offset for inserted channel 0 0 12 04095 IOFF1 IOFF1 Inserted channel data offset register 1 0x18 0x20 read-write 0x00000000 IOFF Data offset for inserted channel 1 0 12 04095 IOFF2 IOFF2 Inserted channel data offset register 2 0x1C 0x20 read-write 0x00000000 IOFF Data offset for inserted channel 2 0 12 04095 IOFF3 IOFF3 Inserted channel data offset register 3 0x20 0x20 read-write 0x00000000 IOFF Data offset for inserted channel 3 0 12 04095 WDHT WDHT watchdog higher threshold register 0x24 0x20 read-write 0x00000FFF WDHT Analog watchdog higher threshold 0 12 04095 WDLT WDLT watchdog lower threshold register 0x28 0x20 read-write 0x00000000 WDLT Analog watchdog lower threshold 0 12 04095 RSQ0 RSQ0 regular sequence register 0 0x2C 0x20 read-write 0x00000000 RL Regular channel group length 20 4 015 RSQ16 16th conversion in regular sequence 15 5 018 RSQ15 15th conversion in regular sequence 10 5 018 RSQ14 14th conversion in regular sequence 5 5 018 RSQ13 13th conversion in regular sequence 0 5 018 RSQ1 RSQ1 regular sequence register 1 0x30 0x20 read-write 0x00000000 RSQ12 12th conversion in regular sequence 25 5 018 RSQ11 11th conversion in regular sequence 20 5 018 RSQ10 10th conversion in regular sequence 15 5 018 RSQ9 9th conversion in regular sequence 10 5 018 RSQ8 8th conversion in regular sequence 5 5 018 RSQ7 7th conversion in regular sequence 0 5 018 RSQ2 RSQ2 regular sequence register 2 0x34 0x20 read-write 0x00000000 RSQ6 6th conversion in regular sequence 25 5 018 RSQ5 5th conversion in regular sequence 20 5 018 RSQ4 4th conversion in regular sequence 15 5 018 RSQ3 3rd conversion in regular sequence 10 5 018 RSQ2 2nd conversion in regular sequence 5 5 018 RSQ1 1st conversion in regular sequence 0 5 018 ISQ ISQ Inserted sequence register 0x38 0x20 read-write 0x00000000 IL Inserted channel group length 20 2 03 ISQ4 4th conversion in injected sequence 15 5 018 ISQ3 3rd conversion in injected sequence 10 5 018 ISQ2 2nd conversion in injected sequence 5 5 018 ISQ1 1st conversion in injected sequence 0 5 018 IDATA0 IDATA0 injected data register 0 0x3C 0x20 read-only 0x00000000 IDATAn Inserted number n conversion data 0 16 065535 IDATA1 IDATA1 injected data register 1 0x40 0x20 read-only 0x00000000 IDATAn Inserted number n conversion data 0 16 065535 IDATA2 IDATA2 injected data register 2 0x44 0x20 read-only 0x00000000 IDATAn Inserted number n conversion data 0 16 065535 IDATA3 IDATA3 injected data register 3 0x48 0x20 read-only 0x00000000 IDATAn Inserted number n conversion data 0 16 065535 RDATA RDATA regular data register 0x4C 0x20 read-only 0x00000000 RDATA Regular channel data 0 16 065535 CEC HDMI-CEC controller CEC 0x40007800 0x0 0x400 registers CEC 30 CTL CTL control register 0x0 0x20 read-write 0x00000000 ENDOM ENDOM bit value in the next frame in TX mode 2 1 SOM Start of sending a message 1 1 CECEN Enable/disable HDMI-CEC controller 0 1 CFG CFG Configuration register 0x04 0x20 read-write 0x00000000 SFT Signal Free Time 0 3 RTOL Reception bit timing tolerance 3 1 RBRESTP Whether stop receive message when detected RBRE 4 1 RBREGEN Generate Error-bit when detected RBRE in singlecast 5 1 RLBPEGEN Generate Error-bit when detected RLBPE in singlecast 6 1 BCNG Do not generate Error-bit in broadcast message 7 1 SFTOPT The SFT start option 8 1 OADR Own Address 16 15 LMEN Listen mode enable 31 1 TDATA TDATA Transmit data register 0x08 0x20 write-only 0x00000000 TXDATA Tx Data register 0 8 RDATA RDATA Rx Data Register 0x0C 0x20 read-only 0x00000000 RXDATA CEC Rx Data Register 0 8 INTF INTF Interrupt Flag Register 0x10 0x20 read-write 0x00000000 TAERR Tx ACK Error flag 12 1 TERR Tx-Error 11 1 TU Tx data buffer underrun 10 1 TEND Transmission successfully end 9 1 TBR Tx-Byte data request 8 1 LSTARB Arbitration lost 7 1 RAE Rx ACK Error 6 1 RLBPE Long Bit Period Error 5 1 RSBPE Short Bit Period Error 4 1 RBRE Bit Rising Error 3 1 RO RX Overrun 2 1 REND End of Reception 1 1 RBR Rx-Byte data received 0 1 INTEN INTEN interrupt enable register 0x14 0x20 read-write 0x00000000 TAERRIE TAERR Interrupt Enable 12 1 TERRIE TERR Interrupt Enable 11 1 TUIE TU Interrupt Enable 10 1 TXENDIE TEND Interrupt Enable 9 1 TBRIE TBR Interrupt Enable 8 1 LSTARBIE ALRLST Interrupt Enable 7 1 RAEIE RAE Interrupt Enable 6 1 RLBPEIE RLBPE Interrupt Enable 5 1 RSBPEIE RSBPE Interrupt Enable 4 1 RBREIE RBRE Interrupt Enable 3 1 ROIE RO Interrupt Enable 2 1 RENDIE REND Interrupt Enable 1 1 RBRIE RBR Interrupt Enable 0 1 CMP Comparator Comparator 0x4001001C 0x0 0x300 registers CS CS control and status register 0x00 0x20 0x00000000 CMP0EN CMP0 enable 0 1 read-write CMP0ENread-writeDisabledComparator disabled0EnabledComparator enabled1 CMP0SW CMP0 switch 1 1 read-write CMP0SWread-writeOpenSwitch open0ClosedSwitch closed1 CMP0M CMP0 mode 2 2 read-write CMP0Mread-writeHighSpeedHigh speed / full power0MediumSpeedMedium speed / medium power1LowSpeedLow speed / low power2VeryLowSpeedVery-low speed / ultra-low power3 CMP0MSEL CMP0_M input selection 4 3 read-write CMP0MSELread-writeOneQuarterVRef1/4 of VRefint0OneHalfVRef1/2 of VRefint1ThreeQuarterVRef3/4 of VRefint2VRefVRefint3PA4PA4 (DAC04PA5PA55PA0PA06 CMP0OSEL Comparator 0 output selection 8 3 read-write CMP0OSELread-writeNoSelectionNo selection0Timer0BreakInputTimer 0 break input1Timer0InputCapture0Timer 0 Input capture 02Timer0OCPREClearInputTimer 0 OCPRE_CLR input3Timer1InputCapture3Timer 1 input capture 34Timer1OCPREClearInputTimer 1 OCPRE_CLR input5Timer2InputCapture0Timer 2 input capture 06Timer2OCPREClearInputTimer 2 OCPRE_CLR input7 CMP0PL Polarity of CMP0 output 11 1 read-write CMP0PLread-writeNotInvertedOutput is not inverted0InvertedOutput is inverted1 CMP0HST CMP0 hysteresis 12 2 read-write CMP0HSTread-writeNoHysteresisNo hysteresis0LowHysteresisLow hysteresis1MediumHysteresisMedium hysteresis2HighHysteresisHigh hysteresis3 CMP0O CMP0 output 14 1 read-only CMP0Oread-writeLowNon-inverting input below inverting input0HighNon-inverting input above inverting input1 CMP0LK CMP0 lock 15 1 read-write CMP0LKread-writeReadWriteControl bits are read-write0ReadOnlyControl bits are read-only1 CMP1EN CMP1 enable 16 1 read-write CMP1M CMP1 mode 18 2 read-write CMP1MSEL CMP1_M input selection 20 3 read-write WNDEN Window mode enable 23 1 read-write WNDENread-writeDisabledWindow mode disabled0EnabledWindow mode enabled1 CMP1OSEL CMP1 output selection 24 3 read-write CMP1PL Polarity of CMP1 output 27 1 read-write CMP1HST CMP1 hysteresis 28 2 read-write CMP1O CMP1 output 30 1 read-only CMP1LK CMP1 lock 31 1 read-write CRC cyclic redundancy check calculation unit CRC 0x40023000 0x0 0x400 registers DATA DATA Data register 0x0 0x20 read-write 0xFFFFFFFF DATA CRC calculation result 0 32 04294967295 FDATA FDATA Free data register 0x04 0x20 read-write 0x00000000 FDATA Free Data Register bits 0 8 0255 CTL CTL Control register 0x8 0x20 read-write 0x00000000 RST reset bit 0 1 RSTWwriteResetResets the DATA register to IDATA, with no effect on FDATA1 REV_I Input Data Reverse Function 5 2 REV_Iread-writeNormalBit order not affected0ByteBit reversal done by byte1HalfWordBit reversal done by half-word2WordBit reversal done by word3 REV_O Output Data Reverse Function 7 1 REV_Oread-writeNormalBit order not affected0ReversedBit reversed output1 IDATA IDATA Initial CRC value 0x10 0x20 read-write 0xFFFFFFFF IDATA Configurable initial CRC data value 0 32 04294967295 DBG Debug support DBG 0xE0042000 0x0 0x400 registers ID ID MCU Device ID Code Register 0x0 0x20 read-only 0x0 ID_CODE DBG ID code register 0 32 04294967295 CTL0 CTL0 Debug Control Register 0 0x4 0x20 read-write 0x0 SLP_HOLD Sleep mode hold register 0 1 SLP_HOLDread-writeDisabledNo effect0EnabledIn sleep mode the AHB clock is on1 DSLP_HOLD Deep-sleep mode hold register 1 1 DSLP_HOLDread-writeDisabledNo effect0EnabledIn deep-sleep mode the AHB clock and system clock are provided by IRC8M1 STB_HOLD Standby mode hold register 2 1 STB_HOLDread-writeDisabledNo effect0EnabledIn standby mode the AHB clock and system clock are provided by IRC8M1 FWDGT_HOLD FWDGT hold register 8 1 FWDGT_HOLDread-writeContinueContinue running the watchdog timer as usual0StopHold the watchdog timer for debug when the core is halted1 WWDGT_HOLD WWDGT hold register 9 1 TIMER0_HOLD Timer 0 hold register 10 1 TIMER0_HOLDread-writeContinueContinue running the timer as usual0StopHold the timer counter for debug when the core is halted1 TIMER1_HOLD Timer 1 hold register 11 1 TIMER2_HOLD Timer 2 hold register 12 1 I2C0_HOLD I2C0 hold register 15 1 I2C0_HOLDread-writeContinueContinue running I2C as usual0StopHold the I2C timeout for debug when the core is halted1 I2C1_HOLD I2C1 hold register 16 1 I2C2_HOLD I2C2 hold register 17 1 TIMER5_HOLD Timer 5 hold register 19 1 TIMER13_HOLD Timer 13 hold register 27 1 CTL1 CTL1 Debug Control Register 1 0x08 0x20 read-write 0x00000000 RTC_HOLD RTC hold register 10 1 RTC_HOLDread-writeContinueContinue running the RTC as usual0StopHold the RTC for debug when the core is halted1 TIMER14_HOLD Timer 14 hold register 16 1 TIMER14_HOLDread-writeContinueContinue running the timer as usual0StopHold the timer counter for debug when the core is halted1 TIMER15_HOLD Timer 15 hold register 17 1 TIMER16_HOLD Timer 16 hold register 18 1 DMA DMA controller DMA 0x40020000 0x0 0x400 registers DMA_Channel0 9 DMA_Channel1_2 10 DMA_Channel3_4 11 DMA_Channel5_6 48 INTF INTF DMA interrupt flag register (DMA_INTF) 0x0 0x20 read-only 0x00000000 GIF0 Global interrupt flag of channel 0 0 1 GIF0read-writeNoEventNo transfer error, half event, complete event0EventA transfer error, half event or complete event has occured1 FTFIF0 Full transfer finish flag of channel 0 1 1 FTFIF0read-writeNotCompleteNo transfer complete event0CompleteA transfer complete event has occured1 HTFIF0 Half transfer finish flag of channel 0 2 1 HTFIF0read-writeNotHalfNo half transfer event0HalfA half transfer event has occured1 ERRIF0 Transfer access error flag of channel 0 3 1 ERRIF0read-writeNoErrorNo transfer error0ErrorA transfer error has occured1 GIF1 Global interrupt flag of channel 1 4 1 FTFIF1 Full transfer finish flag of channel 1 5 1 HTFIF1 Half transfer finish flag of channel 1 6 1 ERRIF1 Transfer access error flag of channel 1 7 1 GIF2 Global interrupt flag of channel 2 8 1 FTFIF2 Full transfer finish flag of channel 2 9 1 HTFIF2 Half transfer finish flag of channel 2 10 1 ERRIF2 Transfer access error flag of channel 2 11 1 GIF3 Global interrupt flag of channel 3 12 1 FTFIF3 Full transfer finish flag of channel 3 13 1 HTFIF3 Half transfer finish flag of channel 3 14 1 ERRIF3 Transfer access error flag of channel 3 15 1 GIF4 Global interrupt flag of channel 4 16 1 FTFIF4 Full transfer finish flag of channel 4 17 1 HTFIF4 Half transfer finish flag of channel 4 18 1 ERRIF4 Transfer access error flag of channel 4 19 1 GIF5 Global interrupt flag of channel 5 20 1 FTFIF5 Full transfer finish flag of channel 5 21 1 HTFIF5 Half transfer finish flag of channel 5 22 1 ERRIF5 Transfer access error flag of channel 5 23 1 GIF6 Global interrupt flag of channel 6 24 1 FTFIF6 Full transfer finish flag of channel 6 25 1 HTFIF6 Half transfer finish flag of channel 6 26 1 ERRIF6 Transfer access error flag of channel 6 27 1 INTC INTC DMA interrupt flag clear register (DMA_INTC) 0x4 0x20 write-only 0x00000000 GIFC0 Clear global interrupt flag of channel 0 0 1 GIFC0read-writeClearClears the GIF flag in INTF1 GIFC1 Clear global interrupt flag of channel 1 4 1 GIFC2 Clear global interrupt flag of channel 2 8 1 GIFC3 Clear global interrupt flag of channel 3 12 1 GIFC4 Clear global interrupt flag of channel 4 16 1 GIFC5 Clear global interrupt flag of channel 5 20 1 GIFC6 Clear global interrupt flag of channel 6 24 1 FTFIFC0 Clear bit for Full transfer finish flag of channel 0 1 1 FTFIFC0read-writeClearClears the FDFIF flag in INTF1 FTFIFC1 Clear bit for Full transfer finish flag of channel 1 5 1 FTFIFC2 Clear bit for Full transfer finish flag of channel 2 9 1 FTFIFC3 Clear bit for Full transfer finish flag of channel 3 13 1 FTFIFC4 Clear bit for Full transfer finish flag of channel 4 17 1 FTFIFC5 Clear bit for Full transfer finish flag of channel 5 21 1 FTFIFC6 Clear bit for Full transfer finish flag of channel 6 25 1 HTFIFC0 Clear bit for half transfer finish flag of channel 0 2 1 HTFIFC0read-writeClearClears the HTFIF flag in INTF1 HTFIFC1 Clear bit for half transfer finish flag of channel 1 6 1 HTFIFC2 Clear bit for half transfer finish flag of channel 2 10 1 HTFIFC3 Clear bit for half transfer finish flag of channel 3 14 1 HTFIFC4 Clear bit for half transfer finish flag of channel 4 18 1 HTFIFC5 Clear bit for half transfer finish flag of channel 5 22 1 HTFIFC6 Clear bit for half transfer finish flag of channel 6 26 1 ERRIFC0 Clear bit for transfer access error flag of channel 0 3 1 ERRIFC0read-writeClearClears the ERRIF flag in INTF1 ERRIFC1 Clear bit for transfer access error flag of channel 1 7 1 ERRIFC2 Clear bit for transfer access error flag of channel 2 11 1 ERRIFC3 Clear bit for transfer access error flag of channel 3 15 1 ERRIFC4 Clear bit for transfer access error flag of channel 4 19 1 ERRIFC5 Clear bit for transfer access error flag of channel 5 23 1 ERRIFC6 Clear bit for transfer access error flag of channel 6 27 1 CH0CTL CH0CTL0 DMA channel configuration register (DMA_CH0CTL0) 0x8 0x20 read-write 0x00000000 CHEN Channel enable 0 1 CHENread-writeDisabledChannel disabled0EnabledChannel enabled1 FTFIE Enable bit for full transfer finish interrupt 1 1 FTFIEread-writeDisabledFull transfer interrupt disabled0EnabledFull transfer interrupt enabled1 HTFIE Enable bit for half transfer finish interrupt 2 1 HTFIEread-writeDisabledHalf transfer interrupt disabled0EnabledHalf transfer interrupt enabled1 ERRIE Enable bit for tranfer access error interrupt 3 1 ERRIEread-writeDisabledTransfer error interrupt disabled0EnabledTransfer error interrupt enabled1 DIR Transfer mode 4 1 DIRread-writeFromPeripheralRead from peripheral0FromMemoryRead from memory1 CMEN Circular mode enable 5 1 CMENread-writeDisabledCircular buffer disabled0EnabledCircular buffer enabled1 PNAGA Next address generation algorithm of peripheral 6 1 PNAGAread-writeFixedFixed address mode0IncrementIncrement address mode1 MNAGA Next address generation algorithm of memory 7 1 PWIDTH Transfer data size of peripheral 8 2 PWIDTHread-writeBits88-bit size0Bits1616-bit size1Bits3232-bit size2 MWIDTH Transfer data size of memory 10 2 PRIO Priority Level of this channel 12 2 PRIOread-writeLowLow priority0MediumMedium priority1HighHigh priority2VeryHighVery high priority3 M2M Memory to memory mode 14 1 M2Mread-writeDisabledMemory to memory mode disabled0EnabledMemory to memory mode enabled1 CH0CNT CH0CNT DMA channel 0 counter register 0x0C 0x20 read-write 0x00000000 CNT Transfer counter 0 16 065535 CH0PADDR CH0PADDR DMA channel 0 peripheral base address register 0x10 0x20 read-write 0x00000000 PADDR Peripheral base address 0 32 CH0MADDR CH0MADDR DMA channel 0 memory base address register 0x14 0x20 read-write 0x00000000 MADDR Memory base address 0 32 CH1CTL CH1CTL0 DMA channel configuration register (DMA_CH1CTL0) 0x1C 0x20 read-write 0x00000000 CHEN Channel enable 0 1 CHENread-writeDisabledChannel disabled0EnabledChannel enabled1 FTFIE Enable bit for full transfer finish interrupt 1 1 FTFIEread-writeDisabledFull transfer interrupt disabled0EnabledFull transfer interrupt enabled1 HTFIE Enable bit for half transfer finish interrupt 2 1 HTFIEread-writeDisabledHalf transfer interrupt disabled0EnabledHalf transfer interrupt enabled1 ERRIE Enable bit for tranfer access error interrupt 3 1 ERRIEread-writeDisabledTransfer error interrupt disabled0EnabledTransfer error interrupt enabled1 DIR Transfer mode 4 1 DIRread-writeFromPeripheralRead from peripheral0FromMemoryRead from memory1 CMEN Circular mode enable 5 1 CMENread-writeDisabledCircular buffer disabled0EnabledCircular buffer enabled1 PNAGA Next address generation algorithm of peripheral 6 1 PNAGAread-writeFixedFixed address mode0IncrementIncrement address mode1 MNAGA Next address generation algorithm of memory 7 1 PWIDTH Transfer data size of peripheral 8 2 PWIDTHread-writeBits88-bit size0Bits1616-bit size1Bits3232-bit size2 MWIDTH Transfer data size of memory 10 2 PRIO Priority Level of this channel 12 2 PRIOread-writeLowLow priority0MediumMedium priority1HighHigh priority2VeryHighVery high priority3 M2M Memory to memory mode 14 1 M2Mread-writeDisabledMemory to memory mode disabled0EnabledMemory to memory mode enabled1 CH1CNT CH1CNT DMA channel 1 counter register 0x20 0x20 read-write 0x00000000 CNT Transfer counter 0 16 065535 CH1PADDR CH1PADDR DMA channel 1 peripheral base address register 0x24 0x20 read-write 0x00000000 PADDR Peripheral base address 0 32 CH1MADDR CH1MADDR DMA channel 1 memory base address register 0x28 0x20 read-write 0x00000000 MADDR Memory base address 0 32 CH2CTL CH2CTL0 DMA channel configuration register (DMA_CH2CTL0) 0x30 0x20 read-write 0x00000000 CHEN Channel enable 0 1 CHENread-writeDisabledChannel disabled0EnabledChannel enabled1 FTFIE Enable bit for full transfer finish interrupt 1 1 FTFIEread-writeDisabledFull transfer interrupt disabled0EnabledFull transfer interrupt enabled1 HTFIE Enable bit for half transfer finish interrupt 2 1 HTFIEread-writeDisabledHalf transfer interrupt disabled0EnabledHalf transfer interrupt enabled1 ERRIE Enable bit for tranfer access error interrupt 3 1 ERRIEread-writeDisabledTransfer error interrupt disabled0EnabledTransfer error interrupt enabled1 DIR Transfer mode 4 1 DIRread-writeFromPeripheralRead from peripheral0FromMemoryRead from memory1 CMEN Circular mode enable 5 1 CMENread-writeDisabledCircular buffer disabled0EnabledCircular buffer enabled1 PNAGA Next address generation algorithm of peripheral 6 1 PNAGAread-writeFixedFixed address mode0IncrementIncrement address mode1 MNAGA Next address generation algorithm of memory 7 1 PWIDTH Transfer data size of peripheral 8 2 PWIDTHread-writeBits88-bit size0Bits1616-bit size1Bits3232-bit size2 MWIDTH Transfer data size of memory 10 2 PRIO Priority Level of this channel 12 2 PRIOread-writeLowLow priority0MediumMedium priority1HighHigh priority2VeryHighVery high priority3 M2M Memory to memory mode 14 1 M2Mread-writeDisabledMemory to memory mode disabled0EnabledMemory to memory mode enabled1 CH2CNT CH2CNT DMA channel 2 counter register 0x34 0x20 read-write 0x00000000 CNT Transfer counter 0 16 065535 CH2PADDR CH2PADDR DMA channel 2 peripheral base address register 0x38 0x20 read-write 0x00000000 PADDR Peripheral base address 0 32 CH2MADDR CH2MADDR DMA channel 2 memory base address register 0x3C 0x20 read-write 0x00000000 MADDR Memory base address 0 32 CH3CTL CH3CTL0 DMA channel configuration register (DMA_CH3CTL0) 0x44 0x20 read-write 0x00000000 CHEN Channel enable 0 1 CHENread-writeDisabledChannel disabled0EnabledChannel enabled1 FTFIE Enable bit for full transfer finish interrupt 1 1 FTFIEread-writeDisabledFull transfer interrupt disabled0EnabledFull transfer interrupt enabled1 HTFIE Enable bit for half transfer finish interrupt 2 1 HTFIEread-writeDisabledHalf transfer interrupt disabled0EnabledHalf transfer interrupt enabled1 ERRIE Enable bit for tranfer access error interrupt 3 1 ERRIEread-writeDisabledTransfer error interrupt disabled0EnabledTransfer error interrupt enabled1 DIR Transfer mode 4 1 DIRread-writeFromPeripheralRead from peripheral0FromMemoryRead from memory1 CMEN Circular mode enable 5 1 CMENread-writeDisabledCircular buffer disabled0EnabledCircular buffer enabled1 PNAGA Next address generation algorithm of peripheral 6 1 PNAGAread-writeFixedFixed address mode0IncrementIncrement address mode1 MNAGA Next address generation algorithm of memory 7 1 PWIDTH Transfer data size of peripheral 8 2 PWIDTHread-writeBits88-bit size0Bits1616-bit size1Bits3232-bit size2 MWIDTH Transfer data size of memory 10 2 PRIO Priority Level of this channel 12 2 PRIOread-writeLowLow priority0MediumMedium priority1HighHigh priority2VeryHighVery high priority3 M2M Memory to memory mode 14 1 M2Mread-writeDisabledMemory to memory mode disabled0EnabledMemory to memory mode enabled1 CH3CNT CH3CNT DMA channel 3 counter register 0x48 0x20 read-write 0x00000000 CNT Transfer counter 0 16 065535 CH3PADDR CH3PADDR DMA channel 3 peripheral base address register 0x4C 0x20 read-write 0x00000000 PADDR Peripheral base address 0 32 CH3MADDR CH3MADDR DMA channel 3 memory base address register 0x50 0x20 read-write 0x00000000 MADDR Memory base address 0 32 CH4CTL CH4CTL0 DMA channel configuration register (DMA_CH4CTL0) 0x58 0x20 read-write 0x00000000 CHEN Channel enable 0 1 CHENread-writeDisabledChannel disabled0EnabledChannel enabled1 FTFIE Enable bit for full transfer finish interrupt 1 1 FTFIEread-writeDisabledFull transfer interrupt disabled0EnabledFull transfer interrupt enabled1 HTFIE Enable bit for half transfer finish interrupt 2 1 HTFIEread-writeDisabledHalf transfer interrupt disabled0EnabledHalf transfer interrupt enabled1 ERRIE Enable bit for tranfer access error interrupt 3 1 ERRIEread-writeDisabledTransfer error interrupt disabled0EnabledTransfer error interrupt enabled1 DIR Transfer mode 4 1 DIRread-writeFromPeripheralRead from peripheral0FromMemoryRead from memory1 CMEN Circular mode enable 5 1 CMENread-writeDisabledCircular buffer disabled0EnabledCircular buffer enabled1 PNAGA Next address generation algorithm of peripheral 6 1 PNAGAread-writeFixedFixed address mode0IncrementIncrement address mode1 MNAGA Next address generation algorithm of memory 7 1 PWIDTH Transfer data size of peripheral 8 2 PWIDTHread-writeBits88-bit size0Bits1616-bit size1Bits3232-bit size2 MWIDTH Transfer data size of memory 10 2 PRIO Priority Level of this channel 12 2 PRIOread-writeLowLow priority0MediumMedium priority1HighHigh priority2VeryHighVery high priority3 M2M Memory to memory mode 14 1 M2Mread-writeDisabledMemory to memory mode disabled0EnabledMemory to memory mode enabled1 CH4CNT CH4CNT DMA channel 4 counter register 0x5C 0x20 read-write 0x00000000 CNT Transfer counter 0 16 065535 CH4PADDR CH4PADDR DMA channel 4 peripheral base address register 0x60 0x20 read-write 0x00000000 PADDR Peripheral base address 0 32 CH4MADDR CH4MADDR DMA channel 4 memory base address register 0x64 0x20 read-write 0x00000000 MADDR Memory base address 0 32 CH5CTL CH5CTL0 DMA channel configuration register (DMA_CH5CTL0) 0x6C 0x20 read-write 0x00000000 CHEN Channel enable 0 1 CHENread-writeDisabledChannel disabled0EnabledChannel enabled1 FTFIE Enable bit for full transfer finish interrupt 1 1 FTFIEread-writeDisabledFull transfer interrupt disabled0EnabledFull transfer interrupt enabled1 HTFIE Enable bit for half transfer finish interrupt 2 1 HTFIEread-writeDisabledHalf transfer interrupt disabled0EnabledHalf transfer interrupt enabled1 ERRIE Enable bit for tranfer access error interrupt 3 1 ERRIEread-writeDisabledTransfer error interrupt disabled0EnabledTransfer error interrupt enabled1 DIR Transfer mode 4 1 DIRread-writeFromPeripheralRead from peripheral0FromMemoryRead from memory1 CMEN Circular mode enable 5 1 CMENread-writeDisabledCircular buffer disabled0EnabledCircular buffer enabled1 PNAGA Next address generation algorithm of peripheral 6 1 PNAGAread-writeFixedFixed address mode0IncrementIncrement address mode1 MNAGA Next address generation algorithm of memory 7 1 PWIDTH Transfer data size of peripheral 8 2 PWIDTHread-writeBits88-bit size0Bits1616-bit size1Bits3232-bit size2 MWIDTH Transfer data size of memory 10 2 PRIO Priority Level of this channel 12 2 PRIOread-writeLowLow priority0MediumMedium priority1HighHigh priority2VeryHighVery high priority3 M2M Memory to memory mode 14 1 M2Mread-writeDisabledMemory to memory mode disabled0EnabledMemory to memory mode enabled1 CH5CNT CH5CNT DMA channel 5 counter register 0x70 0x20 read-write 0x00000000 CNT Transfer counter 0 16 065535 CH5PADDR CH5PADDR DMA channel 5 peripheral base address register 0x74 0x20 read-write 0x00000000 PADDR Peripheral base address 0 32 CH5MADDR CH5MADDR DMA channel 5 memory base address register 0x78 0x20 read-write 0x00000000 MADDR Memory base address 0 32 CH6CTL CH6CTL0 DMA channel configuration register (DMA_CH6CTL0) 0x80 0x20 read-write 0x00000000 CHEN Channel enable 0 1 CHENread-writeDisabledChannel disabled0EnabledChannel enabled1 FTFIE Enable bit for full transfer finish interrupt 1 1 FTFIEread-writeDisabledFull transfer interrupt disabled0EnabledFull transfer interrupt enabled1 HTFIE Enable bit for full transfer finish interrupt 2 1 HTFIEread-writeDisabledHalf transfer interrupt disabled0EnabledHalf transfer interrupt enabled1 ERRIE Enable bit for tranfer access error interrupt 3 1 ERRIEread-writeDisabledTransfer error interrupt disabled0EnabledTransfer error interrupt enabled1 DIR Transfer mode 4 1 DIRread-writeFromPeripheralRead from peripheral0FromMemoryRead from memory1 CMEN Circular mode enable 5 1 CMENread-writeDisabledCircular buffer disabled0EnabledCircular buffer enabled1 PNAGA Next address generation algorithm of peripheral 6 1 PNAGAread-writeFixedFixed address mode0IncrementIncrement address mode1 MNAGA Next address generation algorithm of memory 7 1 PWIDTH Transfer data size of peripheral 8 2 PWIDTHread-writeBits88-bit size0Bits1616-bit size1Bits3232-bit size2 MWIDTH Transfer data size of memory 10 2 PRIO Priority Level of this channel 12 2 PRIOread-writeLowLow priority0MediumMedium priority1HighHigh priority2VeryHighVery high priority3 M2M Memory to memory mode 14 1 M2Mread-writeDisabledMemory to memory mode disabled0EnabledMemory to memory mode enabled1 CH6CNT CH6CNT DMA channel 6 counter register 0x84 0x20 read-write 0x00000000 CNT Transfer counter 0 16 065535 CH6PADDR CH6PADDR DMA channel 6 peripheral base address register 0x88 0x20 read-write 0x00000000 PADDR Peripheral base address 0 32 CH6MADDR CH6MADDR DMA channel 6 memory base address register 0x8C 0x20 read-write 0x00000000 MADDR Memory base address 0 32 EXTI External interrupt/event controller EXTI 0x40010400 0x0 0x400 registers LVD 1 EXTI0_1 5 EXTI2_3 6 EXTI4_15 7 INTEN INTEN Interrupt enable register (EXTI_INTEN) 0x0 0x20 read-write 0x0F900000 INTEN0 Interrupt mask on line 0 0 1 INTEN0read-writeMaskedInterrupt from line is disabled0UnmaskedInterrupt from line is enabled1 INTEN1 Interrupt mask on line 1 1 1 INTEN2 Interrupt mask on line 2 2 1 INTEN3 Interrupt mask on line 3 3 1 INTEN4 Interrupt mask on line 4 4 1 INTEN5 Interrupt mask on line 5 5 1 INTEN6 Interrupt mask on line 6 6 1 INTEN7 Interrupt mask on line 7 7 1 INTEN8 Interrupt mask on line 8 8 1 INTEN9 Interrupt mask on line 9 9 1 INTEN10 Interrupt mask on line 10 10 1 INTEN11 Interrupt mask on line 11 11 1 INTEN12 Interrupt mask on line 12 12 1 INTEN13 Interrupt mask on line 13 13 1 INTEN14 Interrupt mask on line 14 14 1 INTEN15 Interrupt mask on line 15 15 1 INTEN16 Interrupt mask on line 16 16 1 INTEN17 Interrupt mask on line 17 17 1 INTEN18 Interrupt mask on line 18 18 1 INTEN19 Interrupt mask on line 19 19 1 INTEN20 Interrupt mask on line 20 20 1 INTEN21 Interrupt mask on line 21 21 1 INTEN22 Interrupt mask on line 22 22 1 INTEN23 Interrupt mask on line 23 23 1 INTEN24 Interrupt mask on line 24 24 1 INTEN25 Interrupt mask on line 25 25 1 INTEN26 Interrupt mask on line 26 26 1 INTEN27 Interrupt mask on line 27 27 1 EVEN EVEN Event enable register (EXTI_EVEN) 0x04 0x20 read-write 0x00000000 EVEN0 Event enable on line 0 0 1 EVEN0read-writeMaskedEvent from line is disabled0UnmaskedEvent from line is enabled1 EVEN1 Event enable on line 1 1 1 EVEN2 Event enable on line 2 2 1 EVEN3 Event enable on line 3 3 1 EVEN4 Event enable on line 4 4 1 EVEN5 Event enable on line 5 5 1 EVEN6 Event enable on line 6 6 1 EVEN7 Event enable on line 7 7 1 EVEN8 Event enable on line 8 8 1 EVEN9 Event enable on line 9 9 1 EVEN10 Event enable on line 10 10 1 EVEN11 Event enable on line 11 11 1 EVEN12 Event enable on line 12 12 1 EVEN13 Event enable on line 13 13 1 EVEN14 Event enable on line 14 14 1 EVEN15 Event enable on line 15 15 1 EVEN16 Event enable on line 16 16 1 EVEN17 Event enable on line 17 17 1 EVEN18 Event enable on line 18 18 1 EVEN19 Event enable on line 19 19 1 EVEN20 Event enable on line 20 20 1 EVEN21 Event enable on line 21 21 1 EVEN22 Event enable on line 22 22 1 EVEN23 Event enable on line 23 23 1 EVEN24 Event enable on line 24 24 1 EVEN25 Event enable on line 25 25 1 EVEN26 Event enable on line 26 26 1 EVEN27 Event enable on line 27 27 1 RTEN RTEN Rising Edge Trigger Enable register (EXTI_RTEN) 0x08 0x20 read-write 0x00000000 RTEN0 Rising edge trigger enable of line 0 0 1 RTEN0read-writeDisabledRising edge trigger is disabled0EnabledRising edge trigger is enabled1 RTEN1 Rising edge trigger enable of line 1 1 1 RTEN2 Rising edge trigger enable of line 2 2 1 RTEN3 Rising edge trigger enable of line 3 3 1 RTEN4 Rising edge trigger enable of line 4 4 1 RTEN5 Rising edge trigger enable of line 5 5 1 RTEN6 Rising edge trigger enable of line 6 6 1 RTEN7 Rising edge trigger enable of line 7 7 1 RTEN8 Rising edge trigger enable of line 8 8 1 RTEN9 Rising edge trigger enable of line 9 9 1 RTEN10 Rising edge trigger enable of line 10 10 1 RTEN11 Rising edge trigger enable of line 11 11 1 RTEN12 Rising edge trigger enable of line 12 12 1 RTEN13 Rising edge trigger enable of line 13 13 1 RTEN14 Rising edge trigger enable of line 14 14 1 RTEN15 Rising edge trigger enable of line 15 15 1 RTEN16 Rising edge trigger enable of line 16 16 1 RTEN17 Rising edge trigger enable of line 17 17 1 RTEN18 Rising edge trigger enable of line 18 18 1 RTEN19 Rising edge trigger enable of line 19 19 1 RTEN21 Rising edge trigger enable of line 21 21 1 RTEN22 Rising edge trigger enable of line 22 22 1 FTEN FTEN Falling Egde Trigger Enable register (EXTI_FTEN) 0x0C 0x20 read-write 0x00000000 FTEN0 Falling edge trigger enable of line 0 0 1 FTEN0read-writeDisabledFalling edge trigger is disabled0EnabledFalling edge trigger is enabled1 FTEN1 Falling edge trigger enable of line 1 1 1 FTEN2 Falling edge trigger enable of line 2 2 1 FTEN3 Falling edge trigger enable of line 3 3 1 FTEN4 Falling edge trigger enable of line 4 4 1 FTEN5 Falling edge trigger enable of line 5 5 1 FTEN6 Falling edge trigger enable of line 6 6 1 FTEN7 Falling edge trigger enable of line 7 7 1 FTEN8 Falling edge trigger enable of line 8 8 1 FTEN9 Falling edge trigger enable of line 9 9 1 FTEN10 Falling edge trigger enable of line 10 10 1 FTEN11 Falling edge trigger enable of line 11 11 1 FTEN12 Falling edge trigger enable of line 12 12 1 FTEN13 Falling edge trigger enable of line 13 13 1 FTEN14 Falling edge trigger enable of line 14 14 1 FTEN15 Falling edge trigger enable of line 15 15 1 FTEN16 Falling edge trigger enable of line 16 16 1 FTEN17 Falling edge trigger enable of line 17 17 1 FTEN18 Falling edge trigger enable of line 18 18 1 FTEN19 Falling edge trigger enable of line 19 19 1 FTEN21 Falling edge trigger enable of line 21 21 1 FTEN22 Falling edge trigger enable of line 22 22 1 SWIEV SWIEV Software interrupt event register (EXTI_SWIEV) 0x10 0x20 read-write 0x00000000 SWIEV0 Interrupt/Event software trigger on line 0 0 1 SWIEV0WwritePendGenerates an interrupt request1 SWIEV1 Interrupt/Event software trigger on line 1 1 1 SWIEV2 Interrupt/Event software trigger on line 2 2 1 SWIEV3 Interrupt/Event software trigger on line 3 3 1 SWIEV4 Interrupt/Event software trigger on line 4 4 1 SWIEV5 Interrupt/Event software trigger on line 5 5 1 SWIEV6 Interrupt/Event software trigger on line 6 6 1 SWIEV7 Interrupt/Event software trigger on line 7 7 1 SWIEV8 Interrupt/Event software trigger on line 8 8 1 SWIEV9 Interrupt/Event software trigger on line 9 9 1 SWIEV10 Interrupt/Event software trigger on line 10 10 1 SWIEV11 Interrupt/Event software trigger on line 11 11 1 SWIEV12 Interrupt/Event software trigger on line 12 12 1 SWIEV13 Interrupt/Event software trigger on line 13 13 1 SWIEV14 Interrupt/Event software trigger on line 14 14 1 SWIEV15 Interrupt/Event software trigger on line 15 15 1 SWIEV16 Interrupt/Event software trigger on line 16 16 1 SWIEV17 Interrupt/Event software trigger on line 17 17 1 SWIEV18 Interrupt/Event software trigger on line 18 18 1 SWIEV19 Interrupt/Event software trigger on line 19 19 1 SWIEV21 Interrupt/Event software trigger on line 21 21 1 SWIEV22 Interrupt/Event software trigger on line 22 22 1 PD PD Pending register (EXTI_PD) 0x14 0x20 read-write 0x00000000 PD0 Interrupt pending status of line 0 0 1 PD0RreadNotPendingNo trigger request occurred0PendingSelected trigger request occurred1 PD0WwriteClearClears pending bit1 PD1 Interrupt pending status of line 1 1 1 PD2 Interrupt pending status of line 2 2 1 PD3 Interrupt pending status of line 3 3 1 PD4 Interrupt pending status of line 4 4 1 PD5 Interrupt pending status of line 5 5 1 PD6 Interrupt pending status of line 6 6 1 PD7 Interrupt pending status of line 7 7 1 PD8 Interrupt pending status of line 8 8 1 PD9 Interrupt pending status of line 9 9 1 PD10 Interrupt pending status of line 10 10 1 PD11 Interrupt pending status of line 11 11 1 PD12 Interrupt pending status of line 12 12 1 PD13 Interrupt pending status of line 13 13 1 PD14 Interrupt pending status of line 14 14 1 PD15 Interrupt pending status of line 15 15 1 PD16 Interrupt pending status of line 16 16 1 PD17 Interrupt pending status of line 17 17 1 PD18 Interrupt pending status of line 18 18 1 PD19 Interrupt pending status of line 19 19 1 PD21 Interrupt pending status of line 21 21 1 PD22 Interrupt pending status of line 22 22 1 FMC FMC FMC 0x40022000 0x0 0x400 registers FMC 3 WS WS Wait state register 0x0 0x20 0x00000000 WSCNT Wait state counter register 0 3 read-write WSCNTread-writeWS00 wait states added0WS11 wait state added1WS22 wait states added2 KEY KEY Flash unlock key register 0x04 0x20 write-only 0x00000000 KEY FMC_CTL unlock registers 0 32 04294967295 OBKEY OBKEY Flash option byte unlock key register 0x08 0x20 write-only 0x00000000 OBKEY FMC_CTL option byte operation unlock registers 0 32 04294967295 STAT STAT Flash status register 0xC 0x20 0x00000000 ENDF End of operation flag bit 5 1 read-write ENDFRreadNoEventNo end of operation occurred0EventAn end of operation event occurred1 ENDFWwriteClearClears flag1 WPERR Erase/Program protection error flag bit 4 1 read-write WPERRRreadNoErrorThere was no error0ErrorThere was an error erasing/programming protected pages1 WPERRWwriteClearClears flag1 PGERR Program error flag bit 2 1 read-write PGERRRreadNoErrorThere was no error0ErrorThere was an error programming flash1 PGERRWwriteClearClears flag1 BUSY The flash busy bit 0 1 read-only BUSYRreadInactiveNo operation is in progress0ActiveAn operation is in progress1 CTL CTL Flash control register 0x10 0x20 read-write 0x00000080 OBRLD Option byte reload bit 13 1 OBRLDread-writeReloadForce option bytes reload and reset1 ENDIE End of operation interrupt enable 12 1 ENDIEread-writeDisabledEnd of operation interrupt disabled0EnabledEnd of operation interrupt enabled1 ERRIE Error interrupt enable 10 1 ERRIEread-writeDisabledError interrupt generation disabled0EnabledError interrupt generation enabled1 OBWEN Option byte erase/program enable bit 9 1 OBWENRreadDisabledOption byte write disabled0EnabledOption byte write enabled1 OBWENWwriteDisableDisable option byte write0 LK FMC_CTL lock bit 7 1 LKRreadUnlockedCTL register is unlocked0LockedCTL register is locked1 LKWwriteLockLock CTL register1 START Send erase command to FMC bit 6 1 STARTWwriteStartTrigger an erase operation1 OBER Option byte erase command bit 5 1 OBERread-writeOptionByteEraseErase option byte activated1 OBPG Option byte program command bit 4 1 OBPGread-writeOptionByteProgrammingProgram option byte activated1 MER Main flash mass erase command bit 2 1 MERread-writeMassEraseErase activated for all user sectors1 PER Main flash page erase command bit 1 1 PERread-writePageEraseErase activated for selected page1 PG Main flash page program command bit 0 1 PGread-writeProgramFlash programming activated1 ADDR ADDR Flash address register 0x14 0x20 read-write 0x00000000 ADDR Flash command address 0 32 04294967295 OBSTAT OBSTAT Option byte status register 0x1C 0x20 read-only 0x00000000 OB_DATA Store OB_DATA[15:0] of option byte block after system reset 16 16 065535 OB_USER Store OB_USER byte of option byte block after system reset 8 8 0255 PLEVEL Security Protection level 1 2 PLEVELread-writeNoneNo protection level0LowLow protection level1HighHigh protection level3 OBERR Option byte read error 0 1 OBERRread-writeNoErrorNo error with option bytes0ErrorOption bytes and complement bytes do not match1 WP WP Write protection register 0x20 0x20 read-only 0x00000000 OB_WP Store OB_WP[15:0] of option byte block after system reset 0 16 065535 WSEN WSEN Flash wait state control register 0xFC 0x20 read-only 0x00000000 WSEN FMC wait state enable register 0 1 WSENread-writeNoWaitStateNo wait state added0WaitStateWait state added1 BPEN FMC bit program enable register 1 1 PID PID Flash Product ID register 0x100 0x20 read-only 0x00000000 PID Product reserved ID code register1 0 32 04294967295 FWDGT free watchdog timer FWDGT 0x40003000 0x0 0x400 registers CTL CTL Control register 0x00 0x10 write-only 0x00000000 CMD Key value 0 16 CMDread-writeEnableEnable access to PR, RLR and WINR registers (0x5555)21845ResetReset the watchdog value (0xAAAA)43690StartStart the watchdog (0xCCCC)52428 PSC PSC Prescaler register 0x04 0x20 read-write 0x00000000 PSC Free watchdog timer prescaler selection 0 3 PSCread-writeDivideBy4Divider /40DivideBy8Divider /81DivideBy16Divider /162DivideBy32Divider /323DivideBy64Divider /644DivideBy128Divider /1285DivideBy256Divider /2566DivideBy256bisDivider /2567 RLD RLD Reload register 0x08 0x20 read-write 0x00000FFF RLD Free watchdog timer counter reload value 0 12 04095 STAT STAT Status register 0x0C 0x20 read-only 0x00000000 PUD Free watchdog timer prescaler value update 0 1 PUDread-writeValidThe value read from the PSC register is valid0OngoingA write operation to to the PSC register is ongoing, so the value read is invalid1 RUD Free watchdog timer counter reload value update 1 1 RUDread-writeValidThe value read from the RLD register is valid0OngoingA write operation to to the RLD register is ongoing, so the value read is invalid1 WUD Watchdog counter window value update 2 1 WUDread-writeValidThe value read from the WND register is valid0OngoingA write operation to to the WND register is ongoing, so the value read is invalid1 WND WND Window register 0x10 0x20 read-only 0x00000000 WND Watchdog counter window value 0 12 04095 GPIOA General-purpose I/Os GPIO 0x48000000 0x0 0x400 registers CTL CTL GPIO port control register 0x0 0x20 read-write 0x28000000 CTL15 Pin 15 configuration bits 30 2 CTL14 Pin 14 configuration bits 28 2 CTL13 Pin 13 configuration bits 26 2 CTL12 Pin 12 configuration bits 24 2 CTL11 Pin 11 configuration bits 22 2 CTL10 Pin 10 configuration bits 20 2 CTL9 Pin 9 configuration bits 18 2 CTL8 Pin 8 configuration bits 16 2 CTL7 Pin 7 configuration bits 14 2 CTL6 Pin 6 configuration bits 12 2 CTL5 Pin 5 configuration bits 10 2 CTL4 Pin 4 configuration bits 8 2 CTL3 Pin 3 configuration bits 6 2 CTL2 Pin 2 configuration bits 4 2 CTL1 Pin 1 configuration bits 2 2 CTL0 Pin 0 configuration bits 0 2 CTL0read-writeInputInput mode (reset state)0OutputGeneral purpose output mode1AlternateAlternate function mode2AnalogAnalog mode3 OMODE OMODE GPIO port output type register 0x04 0x20 read-write 0x00000000 OM15 Pin 15 output mode 15 1 OM14 Pin 14 output mode 14 1 OM13 Pin 13 output mode 13 1 OM12 Pin 12 output mode 12 1 OM11 Pin 11 output mode 11 1 OM10 Pin 10 output mode 10 1 OM9 Pin 9 output mode 9 1 OM8 Pin 8 output mode 8 1 OM7 Pin 7 output mode 7 1 OM6 Pin 6 output mode 6 1 OM5 Pin 5 output mode 5 1 OM4 Pin 4 output mode 4 1 OM3 Pin 3 output mode 3 1 OM2 Pin 2 output mode 2 1 OM1 Pin 1 output mode 1 1 OM0 Pin 0 output mode 0 1 OM0read-writePushPullOutput push-pull (reset state)0OpenDrainOutput open-drain1 OSPD OSPD GPIO port output speed register 0x08 0x20 read-write 0x0C000000 OSPD15 Pin 15 output max speed bits 30 2 OSPD14 Pin 14 output max speed bits 28 2 OSPD13 Pin 13 output max speed bits 26 2 OSPD12 Pin 12 output max speed bits 24 2 OSPD11 Pin 11 output max speed bits 22 2 OSPD10 Pin 10 output max speed bits 20 2 OSPD9 Pin 9 output max speed bits 18 2 OSPD8 Pin 8 output max speed bits 16 2 OSPD7 Pin 7 output max speed bits 14 2 OSPD6 Pin 6 output max speed bits 12 2 OSPD5 Pin 5 output max speed bits 10 2 OSPD4 Pin 4 output max speed bits 8 2 OSPD3 Pin 3 output max speed bits 6 2 OSPD2 Pin 2 output max speed bits 4 2 OSPD1 Pin 1 output max speed bits 2 2 OSPD0 Pin 0 output max speed bits 0 2 OSPD0read-writeSpeed2MMax output speed 2 MHz0Speed10MMax output speed 10 MHz1Speed50MMax output speed 50 MHz3 PUD PUD GPIO port pull-up/pull-down register 0x0C 0x20 read-write 0x24000000 PUD15 Pin 15 pull-up or pull-down bits 30 2 PUD14 Pin 14 pull-up or pull-down bits 28 2 PUD13 Pin 13 pull-up or pull-down bits 26 2 PUD12 Pin 12 pull-up or pull-down bits 24 2 PUD11 Pin 11 pull-up or pull-down bits 22 2 PUD10 Pin 10 pull-up or pull-down bits 20 2 PUD9 Pin 9 pull-up or pull-down bits 18 2 PUD8 Pin 8 pull-up or pull-down bits 16 2 PUD7 Pin 7 pull-up or pull-down bits 14 2 PUD6 Pin 6 pull-up or pull-down bits 12 2 PUD5 Pin 5 pull-up or pull-down bits 10 2 PUD4 Pin 4 pull-up or pull-down bits 8 2 PUD3 Pin 3 pull-up or pull-down bits 6 2 PUD2 Pin 2 pull-up or pull-down bits 4 2 PUD1 Pin 1 pull-up or pull-down bits 2 2 PUD0 Pin 0 pull-up or pull-down bits 0 2 PUD0read-writeFloatingNo pull-up, pull-down (reset state)0PullUpPull-up1PullDownPull-down2 ISTAT ISTAT GPIO port input data register 0x10 0x20 read-only 0x00000000 ISTAT15 Port input data 14 15 1 ISTAT14 Port input data 14 14 1 ISTAT13 Port input data 13 13 1 ISTAT12 Port input data 12 12 1 ISTAT11 Port input data 11 11 1 ISTAT10 Port input data 10 10 1 ISTAT9 Port input data 9 9 1 ISTAT8 Port input data 8 8 1 ISTAT7 Port input data 7 7 1 ISTAT6 Port input data 6 6 1 ISTAT5 Port input data 5 5 1 ISTAT4 Port input data 4 4 1 ISTAT3 Port input data 3 3 1 ISTAT2 Port input data 2 2 1 ISTAT1 Port input data 1 1 1 ISTAT0 Port input data 0 0 1 ISTAT0read-writeLowInput is logic low0HighInput is logic high1 OCTL OCTL GPIO port output data register 0x14 0x20 read-write 0x00000000 OCTL15 Port output data 15 15 1 OCTL14 Port output data 14 14 1 OCTL13 Port output data 13 13 1 OCTL12 Port output data 12 12 1 OCTL11 Port output data 11 11 1 OCTL10 Port output data 10 10 1 OCTL9 Port output data 9 9 1 OCTL8 Port output data 8 8 1 OCTL7 Port output data 7 7 1 OCTL6 Port output data 6 6 1 OCTL5 Port output data 5 5 1 OCTL4 Port output data 4 4 1 OCTL3 Port output data 3 3 1 OCTL2 Port output data 2 2 1 OCTL1 Port output data 1 1 1 OCTL0 Port output data 0 0 1 OCTL0read-writeLowSet output to logic low0HighSet output to logic high1 BOP BOP GPIO port bit set/reset register 0x18 0x20 write-only 0x00000000 CR15 Port reset bit 15 31 1 CR14 Port reset bit 14 30 1 CR13 Port reset bit 13 29 1 CR12 Port reset bit 12 28 1 CR11 Port reset bit 11 27 1 CR10 Port reset bit 10 26 1 CR9 Port reset bit 9 25 1 CR8 Port reset bit 8 24 1 CR7 Port reset bit 7 23 1 CR6 Port reset bit 6 22 1 CR5 Port reset bit 5 21 1 CR4 Port reset bit 4 20 1 CR3 Port reset bit 3 19 1 CR2 Port reset bit 2 18 1 CR1 Port reset bit 1 17 1 CR0 Port reset bit 0 16 1 CR0WwriteResetResets the corresponding OCTLx bit1 BOP15 Port set bit15 15 1 BOP14 Port set bit 14 14 1 BOP13 Port set bit 13 13 1 BOP12 Port set bit 12 12 1 BOP11 Port set bit 11 11 1 BOP10 Port set bit 10 10 1 BOP9 Port set bit 9 9 1 BOP8 Port set bit 8 8 1 BOP7 Port set bit 7 7 1 BOP6 Port set bit 6 6 1 BOP5 Port set bit 5 5 1 BOP4 Port set bit 4 4 1 BOP3 Port set bit 3 3 1 BOP2 Port set bit 2 2 1 BOP1 Port set bit 1 1 1 BOP0 Port set bit 0 0 1 BOP0WwriteSetSets the corresponding OCTLx bit1 LOCK LOCK GPIO port configuration lock register 0x1C 0x20 read-write 0x00000000 LKK Lock key 16 1 LKKread-writeNotActivePort configuration lock key not active0ActivePort configuration lock key active1 LK15 Port lock bit 15 15 1 LK14 Port lock bit 14 14 1 LK13 Port lock bit 13 13 1 LK12 Port lock bit 12 12 1 LK11 Port lock bit 11 11 1 LK10 Port lock bit 10 10 1 LK10read-writeUnlockedPort configuration not locked0LockedPort configuration locked1 LK9 Port lock bit 9 9 1 LK8 Port lock bit 8 8 1 LK7 Port lock bit 7 7 1 LK6 Port lock bit 6 6 1 LK5 Port lock bit 5 5 1 LK4 Port lock bit 4 4 1 LK3 Port lock bit 3 3 1 LK2 Port lock bit 2 2 1 LK1 Port lock bit 1 1 1 LK0 Port lock bit 0 0 1 LK0read-writeUnlockedPort configuration not locked0LockedPort configuration locked1 AFSEL0 AFSEL0 GPIO alternate function low register 0x20 0x20 read-write 0x00000000 SEL7 Pin 7 alternate function selected 28 4 SEL6 Pin 6 alternate function selected 24 4 SEL5 Pin 5 alternate function selected 20 4 SEL4 Pin 4 alternate function selected 16 4 SEL3 Pin 3 alternate function selected 12 4 SEL2 Pin 2 alternate function selected 8 4 SEL1 Pin 1 alternate function selected 4 4 SEL0 Pin 0 alternate function selected 0 4 SEL0read-writeAF0AF00AF1AF11AF2AF22AF3AF33AF4AF44AF5AF55AF6AF66AF7AF77AF9AF99AF11AF1111 AFSEL1 AFSEL1 GPIO alternate function register 1 0x24 0x20 read-write 0x00000000 SEL15 Pin 15 alternate function selected 28 4 SEL14 Pin 14 alternate function selected 24 4 SEL13 Pin 13 alternate function selected 20 4 SEL12 Pin 12 alternate function selected 16 4 SEL11 Pin 11 alternate function selected 12 4 SEL10 Pin 10 alternate function selected 8 4 SEL9 Pin 9 alternate function selected 4 4 SEL8 Pin 8 alternate function selected 0 4 SEL8read-writeAF0AF00AF1AF11AF2AF22AF3AF33AF4AF44AF5AF55AF6AF66AF7AF77AF9AF99AF11AF1111 BC BC Port bit reset register 0x28 0x20 write-only 0x00000000 CR0 Port cleat bit 0 0 1 CR0WwriteResetResets the corresponding OCTLx bit1 CR1 Port cleat bit 1 1 1 CR2 Port cleat bit 2 2 1 CR3 Port cleat bit 3 3 1 CR4 Port cleat bit 4 4 1 CR5 Port cleat bit 5 5 1 CR6 Port cleat bit 6 6 1 CR7 Port cleat bit 7 7 1 CR8 Port cleat bit 8 8 1 CR9 Port cleat bit 9 9 1 CR10 Port cleat bit 10 10 1 CR11 Port cleat bit 11 11 1 CR12 Port cleat bit 12 12 1 CR13 Port cleat bit 13 13 1 CR14 Port cleat bit 14 14 1 CR15 Port cleat bit 15 15 1 TG TG Port bit toggle register 0x2C 0x20 write-only 0x00000000 TG0 Port toggle bit 0 0 1 TG0WwriteToggleToggles the corresponding OCTLx bit1 TG1 Port toggle bit 1 1 1 TG2 Port toggle bit 2 2 1 TG3 Port toggle bit 3 3 1 TG4 Port toggle bit 4 4 1 TG5 Port toggle bit 5 5 1 TG6 Port toggle bit 6 6 1 TG7 Port toggle bit 7 7 1 TG8 Port toggle bit 8 8 1 TG9 Port toggle bit 9 9 1 TG10 Port toggle bit 10 10 1 TG11 Port toggle bit 11 11 1 TG12 Port toggle bit 12 12 1 TG13 Port toggle bit 13 13 1 TG14 Port toggle bit 14 14 1 TG15 Port toggle bit 15 15 1 GPIOB General-purpose I/Os GPIO 0x48000400 0x0 0x400 registers CTL CTL GPIO port control register 0x0 0x20 read-write 0x00000000 CTL15 Pin 15 configuration bits 30 2 CTL14 Pin 14 configuration bits 28 2 CTL13 Pin 13 configuration bits 26 2 CTL12 Pin 12 configuration bits 24 2 CTL11 Pin 11 configuration bits 22 2 CTL10 Pin 10 configuration bits 20 2 CTL9 Pin 9 configuration bits 18 2 CTL8 Pin 8 configuration bits 16 2 CTL7 Pin 7 configuration bits 14 2 CTL6 Pin 6 configuration bits 12 2 CTL5 Pin 5 configuration bits 10 2 CTL4 Pin 4 configuration bits 8 2 CTL3 Pin 3 configuration bits 6 2 CTL2 Pin 2 configuration bits 4 2 CTL1 Pin 1 configuration bits 2 2 CTL0 Pin 0 configuration bits 0 2 CTL0read-writeInputInput mode (reset state)0OutputGeneral purpose output mode1AlternateAlternate function mode2AnalogAnalog mode3 OMODE OMODE GPIO port output type register 0x04 0x20 read-write 0x00000000 OM15 Pin 15 output mode 15 1 OM14 Pin 14 output mode 14 1 OM13 Pin 13 output mode 13 1 OM12 Pin 12 output mode 12 1 OM11 Pin 11 output mode 11 1 OM10 Pin 10 output mode 10 1 OM9 Pin 9 output mode 9 1 OM8 Pin 8 output mode 8 1 OM7 Pin 7 output mode 7 1 OM6 Pin 6 output mode 6 1 OM5 Pin 5 output mode 5 1 OM4 Pin 4 output mode 4 1 OM3 Pin 3 output mode 3 1 OM2 Pin 2 output mode 2 1 OM1 Pin 1 output mode 1 1 OM0 Pin 0 output mode 0 1 OM0read-writePushPullOutput push-pull (reset state)0OpenDrainOutput open-drain1 OSPD OSPD GPIO port output speed register 0x08 0x20 read-write 0x00000000 OSPD15 Pin 15 output max speed bits 30 2 OSPD14 Pin 14 output max speed bits 28 2 OSPD13 Pin 13 output max speed bits 26 2 OSPD12 Pin 12 output max speed bits 24 2 OSPD11 Pin 11 output max speed bits 22 2 OSPD10 Pin 10 output max speed bits 20 2 OSPD9 Pin 9 output max speed bits 18 2 OSPD8 Pin 8 output max speed bits 16 2 OSPD7 Pin 7 output max speed bits 14 2 OSPD6 Pin 6 output max speed bits 12 2 OSPD5 Pin 5 output max speed bits 10 2 OSPD4 Pin 4 output max speed bits 8 2 OSPD3 Pin 3 output max speed bits 6 2 OSPD2 Pin 2 output max speed bits 4 2 OSPD1 Pin 1 output max speed bits 2 2 OSPD0 Pin 0 output max speed bits 0 2 OSPD0read-writeSpeed2MMax output speed 2 MHz0Speed10MMax output speed 10 MHz1Speed50MMax output speed 50 MHz3 PUD PUD GPIO port pull-up/pull-down register 0x0C 0x20 read-write 0x00000000 PUD15 Pin 15 pull-up or pull-down bits 30 2 PUD14 Pin 14 pull-up or pull-down bits 28 2 PUD13 Pin 13 pull-up or pull-down bits 26 2 PUD12 Pin 12 pull-up or pull-down bits 24 2 PUD11 Pin 11 pull-up or pull-down bits 22 2 PUD10 Pin 10 pull-up or pull-down bits 20 2 PUD9 Pin 9 pull-up or pull-down bits 18 2 PUD8 Pin 8 pull-up or pull-down bits 16 2 PUD7 Pin 7 pull-up or pull-down bits 14 2 PUD6 Pin 6 pull-up or pull-down bits 12 2 PUD5 Pin 5 pull-up or pull-down bits 10 2 PUD4 Pin 4 pull-up or pull-down bits 8 2 PUD3 Pin 3 pull-up or pull-down bits 6 2 PUD2 Pin 2 pull-up or pull-down bits 4 2 PUD1 Pin 1 pull-up or pull-down bits 2 2 PUD0 Pin 0 pull-up or pull-down bits 0 2 PUD0read-writeFloatingNo pull-up, pull-down (reset state)0PullUpPull-up1PullDownPull-down2 ISTAT ISTAT GPIO port input data register 0x10 0x20 read-only 0x00000000 ISTAT15 Port input data 14 15 1 ISTAT14 Port input data 14 14 1 ISTAT13 Port input data 13 13 1 ISTAT12 Port input data 12 12 1 ISTAT11 Port input data 11 11 1 ISTAT10 Port input data 10 10 1 ISTAT9 Port input data 9 9 1 ISTAT8 Port input data 8 8 1 ISTAT7 Port input data 7 7 1 ISTAT6 Port input data 6 6 1 ISTAT5 Port input data 5 5 1 ISTAT4 Port input data 4 4 1 ISTAT3 Port input data 3 3 1 ISTAT2 Port input data 2 2 1 ISTAT1 Port input data 1 1 1 ISTAT0 Port input data 0 0 1 ISTAT0read-writeLowInput is logic low0HighInput is logic high1 OCTL OCTL GPIO port output data register 0x14 0x20 read-write 0x00000000 OCTL15 Port output data 15 15 1 OCTL14 Port output data 14 14 1 OCTL13 Port output data 13 13 1 OCTL12 Port output data 12 12 1 OCTL11 Port output data 11 11 1 OCTL10 Port output data 10 10 1 OCTL9 Port output data 9 9 1 OCTL8 Port output data 8 8 1 OCTL7 Port output data 7 7 1 OCTL6 Port output data 6 6 1 OCTL5 Port output data 5 5 1 OCTL4 Port output data 4 4 1 OCTL3 Port output data 3 3 1 OCTL2 Port output data 2 2 1 OCTL1 Port output data 1 1 1 OCTL0 Port output data 0 0 1 OCTL0read-writeLowSet output to logic low0HighSet output to logic high1 BOP BOP GPIO port bit set/reset register 0x18 0x20 write-only 0x00000000 CR15 Port reset bit 15 31 1 CR14 Port reset bit 14 30 1 CR13 Port reset bit 13 29 1 CR12 Port reset bit 12 28 1 CR11 Port reset bit 11 27 1 CR10 Port reset bit 10 26 1 CR9 Port reset bit 9 25 1 CR8 Port reset bit 8 24 1 CR7 Port reset bit 7 23 1 CR6 Port reset bit 6 22 1 CR5 Port reset bit 5 21 1 CR4 Port reset bit 4 20 1 CR3 Port reset bit 3 19 1 CR2 Port reset bit 2 18 1 CR1 Port reset bit 1 17 1 CR0 Port reset bit 0 16 1 CR0WwriteResetResets the corresponding OCTLx bit1 BOP15 Port set bit15 15 1 BOP14 Port set bit 14 14 1 BOP13 Port set bit 13 13 1 BOP12 Port set bit 12 12 1 BOP11 Port set bit 11 11 1 BOP10 Port set bit 10 10 1 BOP9 Port set bit 9 9 1 BOP8 Port set bit 8 8 1 BOP7 Port set bit 7 7 1 BOP6 Port set bit 6 6 1 BOP5 Port set bit 5 5 1 BOP4 Port set bit 4 4 1 BOP3 Port set bit 3 3 1 BOP2 Port set bit 2 2 1 BOP1 Port set bit 1 1 1 BOP0 Port set bit 0 0 1 BOP0WwriteSetSets the corresponding OCTLx bit1 LOCK LOCK GPIO port configuration lock register 0x1C 0x20 read-write 0x00000000 LKK Lock key 16 1 LKKread-writeNotActivePort configuration lock key not active0ActivePort configuration lock key active1 LK15 Port lock bit 15 15 1 LK14 Port lock bit 14 14 1 LK13 Port lock bit 13 13 1 LK12 Port lock bit 12 12 1 LK11 Port lock bit 11 11 1 LK10 Port lock bit 10 10 1 LK10read-writeUnlockedPort configuration not locked0LockedPort configuration locked1 LK9 Port lock bit 9 9 1 LK8 Port lock bit 8 8 1 LK7 Port lock bit 7 7 1 LK6 Port lock bit 6 6 1 LK5 Port lock bit 5 5 1 LK4 Port lock bit 4 4 1 LK3 Port lock bit 3 3 1 LK2 Port lock bit 2 2 1 LK1 Port lock bit 1 1 1 LK0 Port lock bit 0 0 1 LK0read-writeUnlockedPort configuration not locked0LockedPort configuration locked1 AFSEL0 AFSEL0 GPIO alternate function low register 0x20 0x20 read-write 0x00000000 SEL7 Pin 7 alternate function selected 28 4 SEL6 Pin 6 alternate function selected 24 4 SEL5 Pin 5 alternate function selected 20 4 SEL4 Pin 4 alternate function selected 16 4 SEL3 Pin 3 alternate function selected 12 4 SEL2 Pin 2 alternate function selected 8 4 SEL1 Pin 1 alternate function selected 4 4 SEL0 Pin 0 alternate function selected 0 4 SEL0read-writeAF0AF00AF1AF11AF2AF22AF3AF33AF4AF44AF5AF55AF6AF66AF7AF77AF9AF99AF11AF1111 AFSEL1 AFSEL1 GPIO alternate function register 1 0x24 0x20 read-write 0x00000000 SEL15 Pin 15 alternate function selected 28 4 SEL14 Pin 14 alternate function selected 24 4 SEL13 Pin 13 alternate function selected 20 4 SEL12 Pin 12 alternate function selected 16 4 SEL11 Pin 11 alternate function selected 12 4 SEL10 Pin 10 alternate function selected 8 4 SEL9 Pin 9 alternate function selected 4 4 SEL8 Pin 8 alternate function selected 0 4 SEL8read-writeAF0AF00AF1AF11AF2AF22AF3AF33AF4AF44AF5AF55AF6AF66AF7AF77AF9AF99AF11AF1111 BC BC Port bit reset register 0x28 0x20 write-only 0x00000000 CR0 Port cleat bit 0 0 1 CR0WwriteResetResets the corresponding OCTLx bit1 CR1 Port cleat bit 1 1 1 CR2 Port cleat bit 2 2 1 CR3 Port cleat bit 3 3 1 CR4 Port cleat bit 4 4 1 CR5 Port cleat bit 5 5 1 CR6 Port cleat bit 6 6 1 CR7 Port cleat bit 7 7 1 CR8 Port cleat bit 8 8 1 CR9 Port cleat bit 9 9 1 CR10 Port cleat bit 10 10 1 CR11 Port cleat bit 11 11 1 CR12 Port cleat bit 12 12 1 CR13 Port cleat bit 13 13 1 CR14 Port cleat bit 14 14 1 CR15 Port cleat bit 15 15 1 TG TG Port bit toggle register 0x2C 0x20 write-only 0x00000000 TG0 Port toggle bit 0 0 1 TG0WwriteToggleToggles the corresponding OCTLx bit1 TG1 Port toggle bit 1 1 1 TG2 Port toggle bit 2 2 1 TG3 Port toggle bit 3 3 1 TG4 Port toggle bit 4 4 1 TG5 Port toggle bit 5 5 1 TG6 Port toggle bit 6 6 1 TG7 Port toggle bit 7 7 1 TG8 Port toggle bit 8 8 1 TG9 Port toggle bit 9 9 1 TG10 Port toggle bit 10 10 1 TG11 Port toggle bit 11 11 1 TG12 Port toggle bit 12 12 1 TG13 Port toggle bit 13 13 1 TG14 Port toggle bit 14 14 1 TG15 Port toggle bit 15 15 1 GPIOC General-purpose I/Os GPIO 0x48000800 0x0 0x400 registers CTL CTL GPIO port control register 0x0 0x20 read-write 0x00000000 CTL15 Port x configuration bits (y = 0..15) 30 2 CTL14 Port x configuration bits (y = 0..15) 28 2 CTL13 Port x configuration bits (y = 0..15) 26 2 CTL12 Port x configuration bits (y = 0..15) 24 2 CTL11 Port x configuration bits (y = 0..15) 22 2 CTL10 Port x configuration bits (y = 0..15) 20 2 CTL9 Port x configuration bits (y = 0..15) 18 2 CTL8 Port x configuration bits (y = 0..15) 16 2 CTL7 Port x configuration bits (y = 0..15) 14 2 CTL6 Port x configuration bits (y = 0..15) 12 2 CTL5 Port x configuration bits (y = 0..15) 10 2 CTL4 Port x configuration bits (y = 0..15) 8 2 CTL3 Port x configuration bits (y = 0..15) 6 2 CTL2 Port x configuration bits (y = 0..15) 4 2 CTL1 Port x configuration bits (y = 0..15) 2 2 CTL0 Port x configuration bits (y = 0..15) 0 2 CTL0read-writeInputInput mode (reset state)0OutputGeneral purpose output mode1AlternateAlternate function mode2AnalogAnalog mode3 OMODE OMODE GPIO port output type register 0x04 0x20 read-write 0x00000000 OM15 Pin 15 output mode 15 1 OM14 Pin 14 output mode 14 1 OM13 Pin 13 output mode 13 1 OM12 Pin 12 output mode 12 1 OM11 Pin 11 output mode 11 1 OM10 Pin 10 output mode 10 1 OM9 Pin 9 output mode 9 1 OM8 Pin 8 output mode 8 1 OM7 Pin 7 output mode 7 1 OM6 Pin 6 output mode 6 1 OM5 Pin 5 output mode 5 1 OM4 Pin 4 output mode 4 1 OM3 Pin 3 output mode 3 1 OM2 Pin 2 output mode 2 1 OM1 Pin 1 output mode 1 1 OM0 Pin 0 output mode 0 1 OM0read-writePushPullOutput push-pull (reset state)0OpenDrainOutput open-drain1 OSPD OSPD GPIO port output speed register 0x08 0x20 read-write 0x00000000 OSPD15 Pin 15 output max speed bits 30 2 OSPD14 Pin 14 output max speed bits 28 2 OSPD13 Pin 13 output max speed bits 26 2 OSPD12 Pin 12 output max speed bits 24 2 OSPD11 Pin 11 output max speed bits 22 2 OSPD10 Pin 10 output max speed bits 20 2 OSPD9 Pin 9 output max speed bits 18 2 OSPD8 Pin 8 output max speed bits 16 2 OSPD7 Pin 7 output max speed bits 14 2 OSPD6 Pin 6 output max speed bits 12 2 OSPD5 Pin 5 output max speed bits 10 2 OSPD4 Pin 4 output max speed bits 8 2 OSPD3 Pin 3 output max speed bits 6 2 OSPD2 Pin 2 output max speed bits 4 2 OSPD1 Pin 1 output max speed bits 2 2 OSPD0 Pin 0 output max speed bits 0 2 OSPD0read-writeSpeed2MMax output speed 2 MHz0Speed10MMax output speed 10 MHz1Speed50MMax output speed 50 MHz3 PUD PUD GPIO port pull-up/pull-down register 0x0C 0x20 read-write 0x00000000 PUD15 Pin 15 pull-up or pull-down bits 30 2 PUD14 Pin 14 pull-up or pull-down bits 28 2 PUD13 Pin 13 pull-up or pull-down bits 26 2 PUD12 Pin 12 pull-up or pull-down bits 24 2 PUD11 Pin 11 pull-up or pull-down bits 22 2 PUD10 Pin 10 pull-up or pull-down bits 20 2 PUD9 Pin 9 pull-up or pull-down bits 18 2 PUD8 Pin 8 pull-up or pull-down bits 16 2 PUD7 Pin 7 pull-up or pull-down bits 14 2 PUD6 Pin 6 pull-up or pull-down bits 12 2 PUD5 Pin 5 pull-up or pull-down bits 10 2 PUD4 Pin 4 pull-up or pull-down bits 8 2 PUD3 Pin 3 pull-up or pull-down bits 6 2 PUD2 Pin 2 pull-up or pull-down bits 4 2 PUD1 Pin 1 pull-up or pull-down bits 2 2 PUD0 Pin 0 pull-up or pull-down bits 0 2 PUD0read-writeFloatingNo pull-up, pull-down (reset state)0PullUpPull-up1PullDownPull-down2 ISTAT ISTAT GPIO port input data register 0x10 0x20 read-only 0x00000000 ISTAT15 Port input data 14 15 1 ISTAT14 Port input data 14 14 1 ISTAT13 Port input data 13 13 1 ISTAT12 Port input data 12 12 1 ISTAT11 Port input data 11 11 1 ISTAT10 Port input data 10 10 1 ISTAT9 Port input data 9 9 1 ISTAT8 Port input data 8 8 1 ISTAT7 Port input data 7 7 1 ISTAT6 Port input data 6 6 1 ISTAT5 Port input data 5 5 1 ISTAT4 Port input data 4 4 1 ISTAT3 Port input data 3 3 1 ISTAT2 Port input data 2 2 1 ISTAT1 Port input data 1 1 1 ISTAT0 Port input data 0 0 1 ISTAT0read-writeLowInput is logic low0HighInput is logic high1 OCTL OCTL GPIO port output data register 0x14 0x20 read-write 0x00000000 OCTL15 Port output data 15 15 1 OCTL14 Port output data 14 14 1 OCTL13 Port output data 13 13 1 OCTL12 Port output data 12 12 1 OCTL11 Port output data 11 11 1 OCTL10 Port output data 10 10 1 OCTL9 Port output data 9 9 1 OCTL8 Port output data 8 8 1 OCTL7 Port output data 7 7 1 OCTL6 Port output data 6 6 1 OCTL5 Port output data 5 5 1 OCTL4 Port output data 4 4 1 OCTL3 Port output data 3 3 1 OCTL2 Port output data 2 2 1 OCTL1 Port output data 1 1 1 OCTL0 Port output data 0 0 1 OCTL0read-writeLowSet output to logic low0HighSet output to logic high1 BOP BOP GPIO port bit set/reset register 0x18 0x20 write-only 0x00000000 CR15 Port reset bit 15 31 1 CR14 Port reset bit 14 30 1 CR13 Port reset bit 13 29 1 CR12 Port reset bit 12 28 1 CR11 Port reset bit 11 27 1 CR10 Port reset bit 10 26 1 CR9 Port reset bit 9 25 1 CR8 Port reset bit 8 24 1 CR7 Port reset bit 7 23 1 CR6 Port reset bit 6 22 1 CR5 Port reset bit 5 21 1 CR4 Port reset bit 4 20 1 CR3 Port reset bit 3 19 1 CR2 Port reset bit 2 18 1 CR1 Port reset bit 1 17 1 CR0 Port reset bit 0 16 1 CR0WwriteResetResets the corresponding OCTLx bit1 BOP15 Port set bit15 15 1 BOP14 Port set bit 14 14 1 BOP13 Port set bit 13 13 1 BOP12 Port set bit 12 12 1 BOP11 Port set bit 11 11 1 BOP10 Port set bit 10 10 1 BOP9 Port set bit 9 9 1 BOP8 Port set bit 8 8 1 BOP7 Port set bit 7 7 1 BOP6 Port set bit 6 6 1 BOP5 Port set bit 5 5 1 BOP4 Port set bit 4 4 1 BOP3 Port set bit 3 3 1 BOP2 Port set bit 2 2 1 BOP1 Port set bit 1 1 1 BOP0 Port set bit 0 0 1 BOP0WwriteSetSets the corresponding OCTLx bit1 AFSEL0 AFSEL0 GPIO alternate function low register 0x20 0x20 read-write 0x00000000 SEL7 Pin 7 alternate function selected 28 4 SEL6 Pin 6 alternate function selected 24 4 SEL5 Pin 5 alternate function selected 20 4 SEL4 Pin 4 alternate function selected 16 4 SEL3 Pin 3 alternate function selected 12 4 SEL2 Pin 2 alternate function selected 8 4 SEL1 Pin 1 alternate function selected 4 4 SEL0 Pin 0 alternate function selected 0 4 SEL0read-writeAF0AF00AF1AF11AF2AF22AF3AF33AF4AF44AF5AF55AF6AF66AF7AF77AF9AF99AF11AF1111 AFSEL1 AFSEL1 GPIO alternate function register 1 0x24 0x20 read-write 0x00000000 SEL15 Pin 15 alternate function selected 28 4 SEL14 Pin 14 alternate function selected 24 4 SEL13 Pin 13 alternate function selected 20 4 SEL12 Pin 12 alternate function selected 16 4 SEL11 Pin 11 alternate function selected 12 4 SEL10 Pin 10 alternate function selected 8 4 SEL9 Pin 9 alternate function selected 4 4 SEL8 Pin 8 alternate function selected 0 4 SEL8read-writeAF0AF00AF1AF11AF2AF22AF3AF33AF4AF44AF5AF55AF6AF66AF7AF77AF9AF99AF11AF1111 BC BC Port bit reset register 0x28 0x20 write-only 0x00000000 CR0 Port cleat bit 0 0 1 CR0WwriteResetResets the corresponding OCTLx bit1 CR1 Port cleat bit 1 1 1 CR2 Port cleat bit 2 2 1 CR3 Port cleat bit 3 3 1 CR4 Port cleat bit 4 4 1 CR5 Port cleat bit 5 5 1 CR6 Port cleat bit 6 6 1 CR7 Port cleat bit 7 7 1 CR8 Port cleat bit 8 8 1 CR9 Port cleat bit 9 9 1 CR10 Port cleat bit 10 10 1 CR11 Port cleat bit 11 11 1 CR12 Port cleat bit 12 12 1 CR13 Port cleat bit 13 13 1 CR14 Port cleat bit 14 14 1 CR15 Port cleat bit 15 15 1 TG TG Port bit toggle register 0x2C 0x20 write-only 0x00000000 TG0 Port toggle bit 0 0 1 TG0WwriteToggleToggles the corresponding OCTLx bit1 TG1 Port toggle bit 1 1 1 TG2 Port toggle bit 2 2 1 TG3 Port toggle bit 3 3 1 TG4 Port toggle bit 4 4 1 TG5 Port toggle bit 5 5 1 TG6 Port toggle bit 6 6 1 TG7 Port toggle bit 7 7 1 TG8 Port toggle bit 8 8 1 TG9 Port toggle bit 9 9 1 TG10 Port toggle bit 10 10 1 TG11 Port toggle bit 11 11 1 TG12 Port toggle bit 12 12 1 TG13 Port toggle bit 13 13 1 TG14 Port toggle bit 14 14 1 TG15 Port toggle bit 15 15 1 GPIOD General-purpose I/Os GPIO 0x48000C00 0x0 0x400 registers CTL CTL GPIO port control register 0x0 0x20 read-write 0x00000000 CTL15 Port x configuration bits (y = 0..15) 30 2 CTL14 Port x configuration bits (y = 0..15) 28 2 CTL13 Port x configuration bits (y = 0..15) 26 2 CTL12 Port x configuration bits (y = 0..15) 24 2 CTL11 Port x configuration bits (y = 0..15) 22 2 CTL10 Port x configuration bits (y = 0..15) 20 2 CTL9 Port x configuration bits (y = 0..15) 18 2 CTL8 Port x configuration bits (y = 0..15) 16 2 CTL7 Port x configuration bits (y = 0..15) 14 2 CTL6 Port x configuration bits (y = 0..15) 12 2 CTL5 Port x configuration bits (y = 0..15) 10 2 CTL4 Port x configuration bits (y = 0..15) 8 2 CTL3 Port x configuration bits (y = 0..15) 6 2 CTL2 Port x configuration bits (y = 0..15) 4 2 CTL1 Port x configuration bits (y = 0..15) 2 2 CTL0 Port x configuration bits (y = 0..15) 0 2 CTL0read-writeInputInput mode (reset state)0OutputGeneral purpose output mode1AlternateAlternate function mode2AnalogAnalog mode3 OMODE OMODE GPIO port output type register 0x04 0x20 read-write 0x00000000 OM15 Pin 15 output mode 15 1 OM14 Pin 14 output mode 14 1 OM13 Pin 13 output mode 13 1 OM12 Pin 12 output mode 12 1 OM11 Pin 11 output mode 11 1 OM10 Pin 10 output mode 10 1 OM9 Pin 9 output mode 9 1 OM8 Pin 8 output mode 8 1 OM7 Pin 7 output mode 7 1 OM6 Pin 6 output mode 6 1 OM5 Pin 5 output mode 5 1 OM4 Pin 4 output mode 4 1 OM3 Pin 3 output mode 3 1 OM2 Pin 2 output mode 2 1 OM1 Pin 1 output mode 1 1 OM0 Pin 0 output mode 0 1 OM0read-writePushPullOutput push-pull (reset state)0OpenDrainOutput open-drain1 OSPD OSPD GPIO port output speed register 0x08 0x20 read-write 0x00000000 OSPD15 Pin 15 output max speed bits 30 2 OSPD14 Pin 14 output max speed bits 28 2 OSPD13 Pin 13 output max speed bits 26 2 OSPD12 Pin 12 output max speed bits 24 2 OSPD11 Pin 11 output max speed bits 22 2 OSPD10 Pin 10 output max speed bits 20 2 OSPD9 Pin 9 output max speed bits 18 2 OSPD8 Pin 8 output max speed bits 16 2 OSPD7 Pin 7 output max speed bits 14 2 OSPD6 Pin 6 output max speed bits 12 2 OSPD5 Pin 5 output max speed bits 10 2 OSPD4 Pin 4 output max speed bits 8 2 OSPD3 Pin 3 output max speed bits 6 2 OSPD2 Pin 2 output max speed bits 4 2 OSPD1 Pin 1 output max speed bits 2 2 OSPD0 Pin 0 output max speed bits 0 2 OSPD0read-writeSpeed2MMax output speed 2 MHz0Speed10MMax output speed 10 MHz1Speed50MMax output speed 50 MHz3 PUD PUD GPIO port pull-up/pull-down register 0x0C 0x20 read-write 0x00000000 PUD15 Pin 15 pull-up or pull-down bits 30 2 PUD14 Pin 14 pull-up or pull-down bits 28 2 PUD13 Pin 13 pull-up or pull-down bits 26 2 PUD12 Pin 12 pull-up or pull-down bits 24 2 PUD11 Pin 11 pull-up or pull-down bits 22 2 PUD10 Pin 10 pull-up or pull-down bits 20 2 PUD9 Pin 9 pull-up or pull-down bits 18 2 PUD8 Pin 8 pull-up or pull-down bits 16 2 PUD7 Pin 7 pull-up or pull-down bits 14 2 PUD6 Pin 6 pull-up or pull-down bits 12 2 PUD5 Pin 5 pull-up or pull-down bits 10 2 PUD4 Pin 4 pull-up or pull-down bits 8 2 PUD3 Pin 3 pull-up or pull-down bits 6 2 PUD2 Pin 2 pull-up or pull-down bits 4 2 PUD1 Pin 1 pull-up or pull-down bits 2 2 PUD0 Pin 0 pull-up or pull-down bits 0 2 PUD0read-writeFloatingNo pull-up, pull-down (reset state)0PullUpPull-up1PullDownPull-down2 ISTAT ISTAT GPIO port input data register 0x10 0x20 read-only 0x00000000 ISTAT15 Port input data 14 15 1 ISTAT14 Port input data 14 14 1 ISTAT13 Port input data 13 13 1 ISTAT12 Port input data 12 12 1 ISTAT11 Port input data 11 11 1 ISTAT10 Port input data 10 10 1 ISTAT9 Port input data 9 9 1 ISTAT8 Port input data 8 8 1 ISTAT7 Port input data 7 7 1 ISTAT6 Port input data 6 6 1 ISTAT5 Port input data 5 5 1 ISTAT4 Port input data 4 4 1 ISTAT3 Port input data 3 3 1 ISTAT2 Port input data 2 2 1 ISTAT1 Port input data 1 1 1 ISTAT0 Port input data 0 0 1 ISTAT0read-writeLowInput is logic low0HighInput is logic high1 OCTL OCTL GPIO port output data register 0x14 0x20 read-write 0x00000000 OCTL15 Port output data 15 15 1 OCTL14 Port output data 14 14 1 OCTL13 Port output data 13 13 1 OCTL12 Port output data 12 12 1 OCTL11 Port output data 11 11 1 OCTL10 Port output data 10 10 1 OCTL9 Port output data 9 9 1 OCTL8 Port output data 8 8 1 OCTL7 Port output data 7 7 1 OCTL6 Port output data 6 6 1 OCTL5 Port output data 5 5 1 OCTL4 Port output data 4 4 1 OCTL3 Port output data 3 3 1 OCTL2 Port output data 2 2 1 OCTL1 Port output data 1 1 1 OCTL0 Port output data 0 0 1 OCTL0read-writeLowSet output to logic low0HighSet output to logic high1 BOP BOP GPIO port bit set/reset register 0x18 0x20 write-only 0x00000000 CR15 Port reset bit 15 31 1 CR14 Port reset bit 14 30 1 CR13 Port reset bit 13 29 1 CR12 Port reset bit 12 28 1 CR11 Port reset bit 11 27 1 CR10 Port reset bit 10 26 1 CR9 Port reset bit 9 25 1 CR8 Port reset bit 8 24 1 CR7 Port reset bit 7 23 1 CR6 Port reset bit 6 22 1 CR5 Port reset bit 5 21 1 CR4 Port reset bit 4 20 1 CR3 Port reset bit 3 19 1 CR2 Port reset bit 2 18 1 CR1 Port reset bit 1 17 1 CR0 Port reset bit 0 16 1 CR0WwriteResetResets the corresponding OCTLx bit1 BOP15 Port set bit15 15 1 BOP14 Port set bit 14 14 1 BOP13 Port set bit 13 13 1 BOP12 Port set bit 12 12 1 BOP11 Port set bit 11 11 1 BOP10 Port set bit 10 10 1 BOP9 Port set bit 9 9 1 BOP8 Port set bit 8 8 1 BOP7 Port set bit 7 7 1 BOP6 Port set bit 6 6 1 BOP5 Port set bit 5 5 1 BOP4 Port set bit 4 4 1 BOP3 Port set bit 3 3 1 BOP2 Port set bit 2 2 1 BOP1 Port set bit 1 1 1 BOP0 Port set bit 0 0 1 BOP0WwriteSetSets the corresponding OCTLx bit1 BC BC Port bit reset register 0x28 0x20 write-only 0x00000000 CR0 Port cleat bit 0 0 1 CR0WwriteResetResets the corresponding OCTLx bit1 CR1 Port cleat bit 1 1 1 CR2 Port cleat bit 2 2 1 CR3 Port cleat bit 3 3 1 CR4 Port cleat bit 4 4 1 CR5 Port cleat bit 5 5 1 CR6 Port cleat bit 6 6 1 CR7 Port cleat bit 7 7 1 CR8 Port cleat bit 8 8 1 CR9 Port cleat bit 9 9 1 CR10 Port cleat bit 10 10 1 CR11 Port cleat bit 11 11 1 CR12 Port cleat bit 12 12 1 CR13 Port cleat bit 13 13 1 CR14 Port cleat bit 14 14 1 CR15 Port cleat bit 15 15 1 TG TG Port bit toggle register 0x2C 0x20 write-only 0x00000000 TG0 Port toggle bit 0 0 1 TG0WwriteToggleToggles the corresponding OCTLx bit1 TG1 Port toggle bit 1 1 1 TG2 Port toggle bit 2 2 1 TG3 Port toggle bit 3 3 1 TG4 Port toggle bit 4 4 1 TG5 Port toggle bit 5 5 1 TG6 Port toggle bit 6 6 1 TG7 Port toggle bit 7 7 1 TG8 Port toggle bit 8 8 1 TG9 Port toggle bit 9 9 1 TG10 Port toggle bit 10 10 1 TG11 Port toggle bit 11 11 1 TG12 Port toggle bit 12 12 1 TG13 Port toggle bit 13 13 1 TG14 Port toggle bit 14 14 1 TG15 Port toggle bit 15 15 1 GPIOF General-purpose I/Os GPIO 0x48001400 0x0 0x400 registers CTL CTL GPIOF port control register 0x0 0x20 read-write 0x00000000 CTL15 Port x configuration bits (y = 0..15) 30 2 CTL14 Port x configuration bits (y = 0..15) 28 2 CTL13 Port x configuration bits (y = 0..15) 26 2 CTL12 Port x configuration bits (y = 0..15) 24 2 CTL11 Port x configuration bits (y = 0..15) 22 2 CTL10 Port x configuration bits (y = 0..15) 20 2 CTL9 Port x configuration bits (y = 0..15) 18 2 CTL8 Port x configuration bits (y = 0..15) 16 2 CTL7 Port x configuration bits (y = 0..15) 14 2 CTL6 Port x configuration bits (y = 0..15) 12 2 CTL5 Port x configuration bits (y = 0..15) 10 2 CTL4 Port x configuration bits (y = 0..15) 8 2 CTL3 Port x configuration bits (y = 0..15) 6 2 CTL2 Port x configuration bits (y = 0..15) 4 2 CTL1 Port x configuration bits (y = 0..15) 2 2 CTL0 Port x configuration bits (y = 0..15) 0 2 CTL0read-writeInputInput mode (reset state)0OutputGeneral purpose output mode1AlternateAlternate function mode2AnalogAnalog mode3 OMODE OMODE GPIO port output type register 0x04 0x20 read-write 0x00000000 OM15 Pin 15 output mode 15 1 OM14 Pin 14 output mode 14 1 OM13 Pin 13 output mode 13 1 OM12 Pin 12 output mode 12 1 OM11 Pin 11 output mode 11 1 OM10 Pin 10 output mode 10 1 OM9 Pin 9 output mode 9 1 OM8 Pin 8 output mode 8 1 OM7 Pin 7 output mode 7 1 OM6 Pin 6 output mode 6 1 OM5 Pin 5 output mode 5 1 OM4 Pin 4 output mode 4 1 OM3 Pin 3 output mode 3 1 OM2 Pin 2 output mode 2 1 OM1 Pin 1 output mode 1 1 OM0 Pin 0 output mode 0 1 OM0read-writePushPullOutput push-pull (reset state)0OpenDrainOutput open-drain1 OSPD OSPD GPIO port output speed register 0x08 0x20 read-write 0x00000000 OSPD15 Pin 15 output max speed bits 30 2 OSPD14 Pin 14 output max speed bits 28 2 OSPD13 Pin 13 output max speed bits 26 2 OSPD12 Pin 12 output max speed bits 24 2 OSPD11 Pin 11 output max speed bits 22 2 OSPD10 Pin 10 output max speed bits 20 2 OSPD9 Pin 9 output max speed bits 18 2 OSPD8 Pin 8 output max speed bits 16 2 OSPD7 Pin 7 output max speed bits 14 2 OSPD6 Pin 6 output max speed bits 12 2 OSPD5 Pin 5 output max speed bits 10 2 OSPD4 Pin 4 output max speed bits 8 2 OSPD3 Pin 3 output max speed bits 6 2 OSPD2 Pin 2 output max speed bits 4 2 OSPD1 Pin 1 output max speed bits 2 2 OSPD0 Pin 0 output max speed bits 0 2 OSPD0read-writeSpeed2MMax output speed 2 MHz0Speed10MMax output speed 10 MHz1Speed50MMax output speed 50 MHz3 PUD PUD GPIO port pull-up/pull-down register 0x0C 0x20 read-write 0x00000000 PUD15 Pin 15 pull-up or pull-down bits 30 2 PUD14 Pin 14 pull-up or pull-down bits 28 2 PUD13 Pin 13 pull-up or pull-down bits 26 2 PUD12 Pin 12 pull-up or pull-down bits 24 2 PUD11 Pin 11 pull-up or pull-down bits 22 2 PUD10 Pin 10 pull-up or pull-down bits 20 2 PUD9 Pin 9 pull-up or pull-down bits 18 2 PUD8 Pin 8 pull-up or pull-down bits 16 2 PUD7 Pin 7 pull-up or pull-down bits 14 2 PUD6 Pin 6 pull-up or pull-down bits 12 2 PUD5 Pin 5 pull-up or pull-down bits 10 2 PUD4 Pin 4 pull-up or pull-down bits 8 2 PUD3 Pin 3 pull-up or pull-down bits 6 2 PUD2 Pin 2 pull-up or pull-down bits 4 2 PUD1 Pin 1 pull-up or pull-down bits 2 2 PUD0 Pin 0 pull-up or pull-down bits 0 2 PUD0read-writeFloatingNo pull-up, pull-down (reset state)0PullUpPull-up1PullDownPull-down2 ISTAT ISTAT GPIO port input data register 0x10 0x20 read-only 0x00000000 ISTAT15 Port input data 14 15 1 ISTAT14 Port input data 14 14 1 ISTAT13 Port input data 13 13 1 ISTAT12 Port input data 12 12 1 ISTAT11 Port input data 11 11 1 ISTAT10 Port input data 10 10 1 ISTAT9 Port input data 9 9 1 ISTAT8 Port input data 8 8 1 ISTAT7 Port input data 7 7 1 ISTAT6 Port input data 6 6 1 ISTAT5 Port input data 5 5 1 ISTAT4 Port input data 4 4 1 ISTAT3 Port input data 3 3 1 ISTAT2 Port input data 2 2 1 ISTAT1 Port input data 1 1 1 ISTAT0 Port input data 0 0 1 ISTAT0read-writeLowInput is logic low0HighInput is logic high1 OCTL OCTL GPIO port output data register 0x14 0x20 read-write 0x00000000 OCTL15 Port output data 15 15 1 OCTL14 Port output data 14 14 1 OCTL13 Port output data 13 13 1 OCTL12 Port output data 12 12 1 OCTL11 Port output data 11 11 1 OCTL10 Port output data 10 10 1 OCTL9 Port output data 9 9 1 OCTL8 Port output data 8 8 1 OCTL7 Port output data 7 7 1 OCTL6 Port output data 6 6 1 OCTL5 Port output data 5 5 1 OCTL4 Port output data 4 4 1 OCTL3 Port output data 3 3 1 OCTL2 Port output data 2 2 1 OCTL1 Port output data 1 1 1 OCTL0 Port output data 0 0 1 OCTL0read-writeLowSet output to logic low0HighSet output to logic high1 BOP BOP GPIO port bit set/reset register 0x18 0x20 write-only 0x00000000 CR15 Port reset bit 15 31 1 CR14 Port reset bit 14 30 1 CR13 Port reset bit 13 29 1 CR12 Port reset bit 12 28 1 CR11 Port reset bit 11 27 1 CR10 Port reset bit 10 26 1 CR9 Port reset bit 9 25 1 CR8 Port reset bit 8 24 1 CR7 Port reset bit 7 23 1 CR6 Port reset bit 6 22 1 CR5 Port reset bit 5 21 1 CR4 Port reset bit 4 20 1 CR3 Port reset bit 3 19 1 CR2 Port reset bit 2 18 1 CR1 Port reset bit 1 17 1 CR0 Port reset bit 0 16 1 CR0WwriteResetResets the corresponding OCTLx bit1 BOP15 Port set bit15 15 1 BOP14 Port set bit 14 14 1 BOP13 Port set bit 13 13 1 BOP12 Port set bit 12 12 1 BOP11 Port set bit 11 11 1 BOP10 Port set bit 10 10 1 BOP9 Port set bit 9 9 1 BOP8 Port set bit 8 8 1 BOP7 Port set bit 7 7 1 BOP6 Port set bit 6 6 1 BOP5 Port set bit 5 5 1 BOP4 Port set bit 4 4 1 BOP3 Port set bit 3 3 1 BOP2 Port set bit 2 2 1 BOP1 Port set bit 1 1 1 BOP0 Port set bit 0 0 1 BOP0WwriteSetSets the corresponding OCTLx bit1 BC BC Port bit reset register 0x28 0x20 write-only 0x00000000 CR0 Port cleat bit 0 0 1 CR0WwriteResetResets the corresponding OCTLx bit1 CR1 Port cleat bit 1 1 1 CR2 Port cleat bit 2 2 1 CR3 Port cleat bit 3 3 1 CR4 Port cleat bit 4 4 1 CR5 Port cleat bit 5 5 1 CR6 Port cleat bit 6 6 1 CR7 Port cleat bit 7 7 1 CR8 Port cleat bit 8 8 1 CR9 Port cleat bit 9 9 1 CR10 Port cleat bit 10 10 1 CR11 Port cleat bit 11 11 1 CR12 Port cleat bit 12 12 1 CR13 Port cleat bit 13 13 1 CR14 Port cleat bit 14 14 1 CR15 Port cleat bit 15 15 1 TG TG Port bit toggle register 0x2C 0x20 write-only 0x00000000 TG0 Port toggle bit 0 0 1 TG0WwriteToggleToggles the corresponding OCTLx bit1 TG1 Port toggle bit 1 1 1 TG2 Port toggle bit 2 2 1 TG3 Port toggle bit 3 3 1 TG4 Port toggle bit 4 4 1 TG5 Port toggle bit 5 5 1 TG6 Port toggle bit 6 6 1 TG7 Port toggle bit 7 7 1 TG8 Port toggle bit 8 8 1 TG9 Port toggle bit 9 9 1 TG10 Port toggle bit 10 10 1 TG11 Port toggle bit 11 11 1 TG12 Port toggle bit 12 12 1 TG13 Port toggle bit 13 13 1 TG14 Port toggle bit 14 14 1 TG15 Port toggle bit 15 15 1 I2C0 Inter integrated circuit I2C 0x40005400 0x0 0x400 registers I2C0_EV 23 I2C0_ER 32 CTL0 CTL0 Control register 0 0x0 0x10 read-write 0x0000 SRESET Software reset I2C 15 1 SRESETread-writeNotResetI2C peripheral not under reset0ResetI2C peripheral under reset1 SALT SMBus alert 13 1 SALTread-writeReleaseSMBA pin released high0DriveSMBA pin driven low1 PECTRANS PEC Transfer 12 1 PECTRANSread-writeDisabledNo PEC transfer0EnabledPEC transfer1 POAP Position of ACK meaning 11 1 POAPread-writeCurrentACK bit controls the (N)ACK of the current byte being received0NextACK bit controls the (N)ACK of the next byte to be received1 ACKEN Whether or not to send an ACK 10 1 ACKENread-writeNAKNo acknowledge returned0ACKAcknowledge returned after a byte is received1 STOP Generate a STOP condition on I2C bus 9 1 STOPread-writeNoStopSTOP will not be sent0StopSTOP will be sent1 START Generate a START condition on I2C bus 8 1 STARTread-writeNoStartSTART will not be sent0StartSTART will be sent1 SS Whether to stretch SCL low when data is not ready in slave mode 7 1 SSread-writeEnabledClock stretching enabled0DisabledClock stretching disabled1 GCEN Whether or not to response to a General Call (0x00) 6 1 GCENread-writeNotRespondSlave won't respond to General Call0RespondSlave will respond to General Call1 PECEN PEC Calculation Switch 5 1 PECENread-writeDisabledPEC calculation disabled0EnabledPEC calculation enabled1 ARPEN ARP protocol in SMBus switch 4 1 ARPENread-writeDisabledARP disabled0EnabledARP enabled1 SMBSEL SMBusType Selection 3 1 SMBSELread-writeDeviceSMBus Device0HostSMBus Host1 SMBEN SMBus/I2C mode switch 1 1 SMBENread-writeI2CI2C Mode0SMBusSMBus1 I2CEN I2C peripheral enable 0 1 I2CENread-writeDisabledPeripheral disabled0EnabledPeripheral enabled1 CTL1 CTL1 Control register 1 0x04 0x10 read-write 0x0000 DMALST Flag indicating DMA last transfer 12 1 DMALSTread-writeNotLastNext DMA EOT is not the last transfer0LastNext DMA EOT is the last transfer1 DMAON DMA mode switch 11 1 DMAONread-writeDisabledDMA requests disabled0EnabledDMA requests enabled1 BUFIE Buffer interrupt enable 10 1 BUFIEread-writeDisabledTBE=1 or RBNE=1 does not generate any interrupt0EnabledTBE=1 or RBNE=1 generates Event interrupt1 EVIE Event interrupt enable 9 1 EVIEread-writeDisabledEvent interrupt disabled0EnabledEvent interrupt enabled1 ERRIE Error interrupt enable 8 1 ERRIEread-writeDisabledError interrupt disabled0EnabledError interrupt enabled1 I2CCLK I2C Peripheral clock frequency 0 6 272 SADDR0 SADDR0 Own address register 0 0x08 0x10 read-write 0x0000 ADDFORMAT Address mode for the I2C slave 15 1 ADDFORMATread-writeAdd77-bit slave address0Add1010-bit slave address1 ADDRESS Interface address 0 10 01023 SADDR1 SADDR1 Own address register 1 0x0C 0x10 read-write 0x0000 ADDRESS2 Second I2C address for the slave in Dual-Address mode 1 7 0127 DUADEN Dual-Address mode switch 0 1 DUADENread-writeSingleSingle addressing mode0DualDual addressing mode1 DATA DATA Data register 0x10 0x10 read-write 0x0000 TRB Transmission or reception data buffer register 0 8 0255 STAT0 STAT0 Transfer status register 0 0x14 0x10 0x0000 SMBALT SMBus Alert status 15 1 read-write SMBALTread-writeNoAlertSMBA not pulled down or no alert occured0AlertSMBA pulled down or alert occurred1 SMBTO Timeout signal in SMBus mode 14 1 read-write SMBTOread-writeNoTimeoutNo Timeout error0TimeoutSCL remained low for 25 ms1 PECERR PEC error when receiving data 12 1 read-write PECERRread-writeNoErrorNo PEC error0ErrorPEC error1 OUERR Over-run or under-run situation occurs in slave mode 11 1 read-write OUERRread-writeNoOverrunNo overrun/underrun occured0OverrunOverrun/underrun occured1 AERR Acknowledge error 10 1 read-write AERRread-writeNoErrorNo acknowledge error0ErrorAcknowledge error1 LOSTARB Arbitration Lost in master mode 9 1 read-write LOSTARBread-writeNoLostNo Arbitration Lost detected0LostArbitration Lost detected1 BERR Bus error 8 1 read-write BERRread-writeNoErrorNo misplaced Start or Stop condition0ErrorMisplaced Start or Stop condition1 TBE I2C_DATA is Empty during transmitting 7 1 read-only TBEread-writeNotEmptyData register not empty0EmptyData register empty, software can write1 RBNE TRBR is not Empty during receiving 6 1 read-only RBNEread-writeEmptyData register empty0NotEmptyData register not empty, software can read1 STPDET STOP condition detected in slave mode 4 1 read-only STPDETread-writeNoStopNo Stop condition detected0StopStop condition detected1 ADD10SEND Header of 10-bit address is sent in master mode 3 1 read-only ADD10SENDread-writeNoHeaderNo header of 10-bit address is sent0HeaderHeader of 10-bit address is sent1 BTC Byte transmission completed 2 1 read-only BTCread-writeNotFinishedData byte transfer not done0FinishedData byte transfer successful1 ADDSEND Address is sent in master mode or received and matches in slave mode 1 1 read-only ADDSENDread-writeNotMatchAdress mismatched or not received0MatchReceived slave address matched with one of the enabled slave addresses1 SBSEND START condition sent out in master mode 0 1 read-only SBSENDread-writeNoStartNo Start condition0StartStart condition generated1 STAT1 STAT1 Transfer status register 1 0x18 0x10 read-only 0x0000 PECV Packet Error Checking Value 8 8 0127 DUMODF Dual Flag in slave mode 7 1 DUMODFread-writeSADDR0The address matches SADDR00SADDR1The address matches SADDR11 HSTSMB SMBus Host Header detected in slave mode 6 1 HSTSMBread-writeNoHeaderNo SMBus host header detected0HeaderSMBus host header detected1 DEFSMB SMBus host header in slave mode 5 1 DEFSMBread-writeNotReceivedDefault address has not been received0ReceivedDefault address has been received1 RXGC General call address (00h) received 4 1 RXGCread-writeNotReceivedNo general call address received0ReceivedGeneral call address received1 TR Whether the I2C is a transmitter or a receiver 2 1 TRread-writeReceiverReceiver0TransmitterTransmitter1 I2CBSY Busy flag 1 1 I2CBSYread-writeNotBusyNo I2C communication0BusyI2C communication active1 MASTER A flag indicating whether I2C block is in master or slave mode 0 1 MASTERread-writeSlaveSlave mode0MasterMaster mode1 CKCFG CKCFG Clock configure register 0x1C 0x10 read-write 0x0000 FAST I2C speed selection in master mode 15 1 FASTread-writeStandardStandard mode I2C0FastFast mode I2C1 DTCY Duty cycle in fast mode 14 1 DTCYread-writeDuty2Duty cycle t_low/t_high = 20Duty16_9Duty cycle t_low/t_high = 16/91 CLKC I2C Clock control in master mode 0 12 04095 RT RT Rise time register 0x20 0x20 read-write 0x0002 RISETIME Maximum rise time in master mode 0 6 0127 I2C1 0x40005800 I2C1_EV 24 I2C1_ER 34 I2C2 0x4000C000 I2C2_EV 35 I2C2_ER 36 NVIC Nested Vectored Interrupt Controller NVIC 0xE000E100 0x0 0xF00 registers 0x33D 0xC3 reserved ISER ISER Interrupt Set Enable Register 0x0 0x20 read-write 0x00000000 SETENA SETENA 0 32 ICER ICER Interrupt Clear Enable Register 0x80 0x20 read-write 0x00000000 CLRENA CLRENA 0 32 ISPR ISPR Interrupt Set-Pending Register 0x100 0x20 read-write 0x00000000 SETPEND SETPEND 0 32 ICPR ICPR Interrupt Clear-Pending Register 0x180 0x20 read-write 0x00000000 CLRPEND CLRPEND 0 32 IABR IABR Interrupt Active bit Register 0x200 0x20 read-write 0x00000000 IABR IABR 0 32 IPR0 IPR0 Interrupt Priority Register 0 0x300 0x08 read-write 0x00 PRI_00 PRI_00 0 8 IPR1 IPR1 Interrupt Priority Register 1 0x301 0x08 read-write 0x00 PRI_01 PRI_01 0 8 IPR2 IPR2 Interrupt Priority Register 2 0x302 0x08 read-write 0x00 PRI_02 PRI_02 0 8 IPR3 IPR3 Interrupt Priority Register 3 0x303 0x08 read-write 0x00 PRI_03 PRI_03 0 8 IPR4 IPR4 Interrupt Priority Register 4 0x304 0x08 read-write 0x00 PRI_04 PRI_04 0 8 IPR5 IPR5 Interrupt Priority Register 5 0x305 0x08 read-write 0x00 PRI_05 PRI_05 0 8 IPR6 IPR6 Interrupt Priority Register 6 0x306 0x08 read-write 0x00 PRI_06 PRI_06 0 8 IPR7 IPR7 Interrupt Priority Register 7 0x307 0x08 read-write 0x00 PRI_07 PRI_07 0 8 IPR8 IPR8 Interrupt Priority Register 8 0x308 0x08 read-write 0x00 PRI_08 PRI_08 0 8 IPR9 IPR9 Interrupt Priority Register 9 0x309 0x08 read-write 0x00 PRI_09 PRI_09 0 8 IPR10 IPR10 Interrupt Priority Register 10 0x30A 0x08 read-write 0x00 PRI_10 PRI_10 0 8 IPR11 IPR11 Interrupt Priority Register 11 0x30B 0x08 read-write 0x00 PRI_11 PRI_11 0 8 IPR12 IPR12 Interrupt Priority Register 12 0x30C 0x08 read-write 0x00 PRI_12 PRI_12 0 8 IPR13 IPR13 Interrupt Priority Register 13 0x30D 0x08 read-write 0x00 PRI_13 PRI_13 0 8 IPR14 IPR14 Interrupt Priority Register 14 0x30E 0x08 read-write 0x00 PRI_14 PRI_14 0 8 IPR15 IPR15 Interrupt Priority Register 15 0x30F 0x08 read-write 0x00 PRI_15 PRI_15 0 8 IPR16 IPR16 Interrupt Priority Register 16 0x310 0x08 read-write 0x00 PRI_16 PRI_16 0 8 IPR17 IPR17 Interrupt Priority Register 17 0x311 0x08 read-write 0x00 PRI_17 PRI_17 0 8 IPR18 IPR18 Interrupt Priority Register 18 0x312 0x08 read-write 0x00 PRI_18 PRI_18 0 8 IPR19 IPR19 Interrupt Priority Register 19 0x313 0x08 read-write 0x00 PRI_19 PRI_19 0 8 IPR20 IPR20 Interrupt Priority Register 20 0x314 0x08 read-write 0x00 PRI_20 PRI_20 0 8 IPR21 IPR21 Interrupt Priority Register 21 0x315 0x08 read-write 0x00 PRI_21 PRI_21 0 8 IPR22 IPR22 Interrupt Priority Register 22 0x316 0x08 read-write 0x00 PRI_22 PRI_22 0 8 IPR23 IPR23 Interrupt Priority Register 23 0x317 0x08 read-write 0x00 PRI_23 PRI_23 0 8 IPR24 IPR24 Interrupt Priority Register 24 0x318 0x08 read-write 0x00 PRI_24 PRI_24 0 8 IPR25 IPR25 Interrupt Priority Register 25 0x319 0x08 read-write 0x00 PRI_25 PRI_25 0 8 IPR26 IPR26 Interrupt Priority Register 26 0x31A 0x08 read-write 0x00 PRI_26 PRI_26 0 8 IPR27 IPR27 Interrupt Priority Register 27 0x31B 0x08 read-write 0x00 PRI_27 PRI_27 0 8 IPR28 IPR28 Interrupt Priority Register 28 0x31C 0x08 read-write 0x00 PRI_28 PRI_28 0 8 IPR29 IPR29 Interrupt Priority Register 29 0x31D 0x08 read-write 0x00 PRI_29 PRI_29 0 8 IPR30 IPR30 Interrupt Priority Register 30 0x31E 0x08 read-write 0x00 PRI_30 PRI_30 0 8 IPR31 IPR31 Interrupt Priority Register 31 0x31F 0x08 read-write 0x00 PRI_31 PRI_31 0 8 IPR32 IPR32 Interrupt Priority Register 32 0x320 0x08 read-write 0x00 PRI_32 PRI_32 0 8 IPR33 IPR33 Interrupt Priority Register 33 0x321 0x08 read-write 0x00 PRI_33 PRI_33 0 8 IPR34 IPR34 Interrupt Priority Register 34 0x322 0x08 read-write 0x00 PRI_34 PRI_34 0 8 IPR35 IPR35 Interrupt Priority Register 35 0x323 0x08 read-write 0x00 PRI_35 PRI_35 0 8 IPR36 IPR36 Interrupt Priority Register 36 0x324 0x08 read-write 0x00 PRI_36 PRI_36 0 8 IPR37 IPR37 Interrupt Priority Register 37 0x325 0x08 read-write 0x00 PRI_37 PRI_37 0 8 IPR38 IPR38 Interrupt Priority Register 38 0x326 0x08 read-write 0x00 PRI_38 PRI_38 0 8 IPR39 IPR39 Interrupt Priority Register 39 0x327 0x08 read-write 0x00 PRI_39 PRI_39 0 8 IPR40 IPR40 Interrupt Priority Register 40 0x328 0x08 read-write 0x00 PRI_40 PRI_40 0 8 IPR41 IPR41 Interrupt Priority Register 41 0x329 0x08 read-write 0x00 PRI_41 PRI_41 0 8 IPR42 IPR42 Interrupt Priority Register 42 0x32A 0x08 read-write 0x00 PRI_42 PRI_42 0 8 IPR43 IPR43 Interrupt Priority Register 43 0x32B 0x08 read-write 0x00 PRI_43 PRI_43 0 8 IPR44 IPR44 Interrupt Priority Register 44 0x32C 0x08 read-write 0x00 PRI_44 PRI_44 0 8 IPR45 IPR45 Interrupt Priority Register 45 0x32D 0x08 read-write 0x00 PRI_45 PRI_45 0 8 IPR46 IPR46 Interrupt Priority Register 46 0x32E 0x08 read-write 0x00 PRI_46 PRI_46 0 8 IPR47 IPR47 Interrupt Priority Register 47 0x32F 0x08 read-write 0x00 PRI_47 PRI_47 0 8 IPR48 IPR48 Interrupt Priority Register 48 0x330 0x08 read-write 0x00 PRI_48 PRI_48 0 8 IPR49 IPR49 Interrupt Priority Register 49 0x331 0x08 read-write 0x00 PRI_49 PRI_49 0 8 IPR50 IPR50 Interrupt Priority Register 50 0x332 0x08 read-write 0x00 PRI_50 PRI_50 0 8 IPR51 IPR51 Interrupt Priority Register 51 0x333 0x08 read-write 0x00 PRI_51 PRI_51 0 8 IPR52 IPR52 Interrupt Priority Register 52 0x334 0x08 read-write 0x00 PRI_52 PRI_52 0 8 IPR53 IPR53 Interrupt Priority Register 53 0x335 0x08 read-write 0x00 PRI_53 PRI_53 0 8 IPR54 IPR54 Interrupt Priority Register 54 0x336 0x08 read-write 0x00 PRI_54 PRI_54 0 8 IPR55 IPR55 Interrupt Priority Register 55 0x337 0x08 read-write 0x00 PRI_55 PRI_55 0 8 IPR56 IPR56 Interrupt Priority Register 56 0x338 0x08 read-write 0x00 PRI_56 PRI_56 0 8 IPR57 IPR57 Interrupt Priority Register 57 0x339 0x08 read-write 0x00 PRI_57 PRI_57 0 8 IPR58 IPR58 Interrupt Priority Register 58 0x33A 0x08 read-write 0x00 PRI_58 PRI_58 0 8 IPR59 IPR59 Interrupt Priority Register 59 0x33B 0x08 read-write 0x00 PRI_59 PRI_59 0 8 IPR60 IPR60 Interrupt Priority Register 60 0x33C 0x08 read-write 0x00 PRI_60 PRI_60 0 8 IPR61 IPR61 Interrupt Priority Register 61 0x33D 0x08 read-write 0x00 PRI_61 PRI_61 0 8 IPR62 IPR62 Interrupt Priority Register 62 0x33E 0x08 read-write 0x00 PRI_62 PRI_62 0 8 IPR63 IPR63 Interrupt Priority Register 63 0x33F 0x08 read-write 0x00 PRI_63 PRI_63 0 8 IPR64 IPR64 Interrupt Priority Register 64 0x340 0x08 read-write 0x00 PRI_64 PRI_64 0 8 IPR65 IPR65 Interrupt Priority Register 65 0x341 0x08 read-write 0x00 PRI_65 PRI_65 0 8 IPR66 IPR66 Interrupt Priority Register 66 0x342 0x08 read-write 0x00 PRI_66 PRI_66 0 8 IPR67 IPR67 Interrupt Priority Register 67 0x343 0x08 read-write 0x00 PRI_67 PRI_67 0 8 IPR68 IPR68 Interrupt Priority Register 68 0x344 0x08 read-write 0x00 PRI_68 PRI_68 0 8 IPR69 IPR69 Interrupt Priority Register 69 0x345 0x08 read-write 0x00 PRI_69 PRI_69 0 8 IPR70 IPR70 Interrupt Priority Register 70 0x346 0x08 read-write 0x00 PRI_70 PRI_70 0 8 IPR71 IPR71 Interrupt Priority Register 71 0x347 0x08 read-write 0x00 PRI_71 PRI_71 0 8 IPR72 IPR72 Interrupt Priority Register 72 0x348 0x08 read-write 0x00 PRI_72 PRI_72 0 8 IPR73 IPR73 Interrupt Priority Register 73 0x349 0x08 read-write 0x00 PRI_73 PRI_73 0 8 STIR STIR Software Trigger Interrupt Register 0xE00 0x20 write-only 0x00000000 STIR STIR 0 32 OPA_IVREF OPA_IVREF OPA_IVREF 0x40007C00 0x0 0x400 registers IVREF_CTL IVREF_CTL IVREF control register 0x300 0x20 0x10000F00 CSDT Current step data 0 6 read-write 063 SCMOD Sink current mode 7 1 read-write SCMODread-writeSourceSource current0SinkSink current1 CPT Current precision trim 8 5 read-write CPTread-writeMinus15Trim -15%0Minus14Trim -14%1Minus13Trim -13%2Minus12Trim -12%3Minus11Trim -11%4Minus10Trim -10%5Minus9Trim -9%6Minus8Trim -8%7Minus7Trim -7%8Minus6Trim -6%9Minus5Trim -5%10Minus4Trim -4%11Minus3Trim -3%12Minus2Trim -2%13Minus1Trim -1%14ZeroTrim 0%15Plus1Trim +1%16Plus2Trim +2%17Plus3Trim +3%18Plus4Trim +4%19Plus5Trim +5%20Plus6Trim +6%21Plus7Trim +7%22Plus8Trim +8%23Plus9Trim +9%24Plus10Trim +10%25Plus11Trim +11%26Plus12Trim +12%27Plus13Trim +13%28Plus14Trim +14%29Plus15Trim +15%30Plus16Trim +16%31 SSEL Step selection 14 1 read-write SSELread-writeLowPowerLow power, 1uA step0HighPowerLow power, 8uA step1 CREN Current reference enable 15 1 read-write CRENread-writeDisabledDisable current reference0EnabledEnable current reference1 VPT Voltage precision tirm 24 5 read-write VPTread-writeMinus6_4Trim -6.4%0Minus6_0Trim -6.0%1Minus5_6Trim -5.6%2Minus5_2Trim -5.2%3Minus4_8Trim -4.8%4Minus4_4Trim -4.4%5Minus4_0Trim -4.0%6Minus3_6Trim -3.6%7Minus3_2Trim -3.2%8Minus2_8Trim -2.8%9Minus2_4Trim -2.4%10Minus2_0Trim -2.0%11Minus1_6Trim -1.6%12Minus1_2Trim -1.2%13Minus0_8Trim -0.8%14Minus0_4Trim -0.4%15ZeroTrim 0%16Plus0_4Trim +0.4%17Plus0_8Trim +0.8%18Plus1_2Trim +1.2%19Plus1_6Trim +1.6%20Plus2_4Trim +2.4%22Plus2_0Trim +2.0%21Plus2_8Trim +2.8%23Plus3_2Trim +3.2%24Plus3_6Trim +3.6%25Plus4_0Trim +4.0%26Plus4_4Trim +4.4%27Plus4_8Trim +4.8%28Plus5_2Trim +5.2%29Plus5_6Trim +5.6%30Plus6_0Trim +6.0%31 DECAP Disconnect external capacitor 30 1 read-write DECAPread-writeConnectedExternal capacitor connected0DisconnectedExternal capacitor disonnected1 VREN Voltage reference enable 31 1 read-write VRENread-writeDisabledDisable voltage reference0EnabledEnable voltage reference1 PMU Power management unit PMU 0x40007000 0x0 0x400 registers CTL CTL power control register 0x0 0x20 read-write 0x00000000 BKPWEN Backup Domain Write Enable 8 1 BKPWENread-writeDisabledAccess to backup domain registers disabled0EnabledAccess to backup domain registers enabled1 LVDT Low Voltage Detector Threshold 5 3 LVDTread-writeV2_22.2 V0V2_32.3 V1V2_42.4 V2V2_52.5 V3V2_62.6 V4V2_72.7 V5V2_82.8 V6V2_92.9 V7 LVDEN Low Voltage Detector Enable 4 1 LVDENread-writeDisabledLow voltage detector disabled0EnabledLow voltage detector enabled1 STBRST Standby Flag Reset 3 1 STBRSTWwriteClearClear the standby flag1 WURST Wakeup Flag Reset 2 1 WURSTWwriteClearClear the wakeup flag1 STBMOD Standby Mode 1 1 STBMODread-writeDeepSleepEnter Deep-sleep mode when the CPU enters deepsleep0StandbyEnter Standby mode when the CPU enters deepsleep1 LDOLP LDO Low Power Mode 0 1 LDOLPread-writeNormalLDO operates normally during Deepsleep mode0LowPowerLDO in low-power mode during Deepsleep mode1 CS CS power control/status register 0x04 0x20 0x00000000 WUPEN1 WKUPN1 Pin Enable 9 1 read-write WUPEN1read-writeDisabledWKUP pin 1 is used for general purpose I/Os. An event on the WKUP pin 1 does not wakeup the device from Standby mode0EnabledWKUP pin 1 is used for wakeup from Standby mode and forced in input pull down configuration (rising edge on WKUP pin 1 wakes-up the system from Standby mode)1 WUPEN0 Enable WKUP pin 8 1 read-write WUPEN0read-writeDisabledWKUP pin 0 is used for general purpose I/Os. An event on the WKUP pin 0 does not wakeup the device from Standby mode0EnabledWKUP pin 0 is used for wakeup from Standby mode and forced in input pull down configuration (rising edge on WKUP pin 0 wakes-up the system from Standby mode)1 LVDF Low Voltage Detector Status Flag 2 1 read-only LVDFRreadAboveThresholdVDD is higher than the LVD threshold0BelowThresholdVDD is lower than or equal to the LVD threshold1 STBF Standby flag 1 1 read-only STBFRreadNoStandbyEventDevice has not been in Standby mode0StandbyEventDevice has been in Standby mode1 WUF Wakeup flag 0 1 read-only WUFRreadNoWakeupEventNo wakeup event occurred0WakeupEventA wakeup event was received from the WKUP pin or from the RTC wakeup event (RTC Tamper event, RTC TimeStamp event or RTC alarm)1 RCU Reset and clock unit RCU 0x40021000 0x0 0x400 registers RCU 4 CTL0 CTL0 Control register 0 0x0 0x20 0x00000083 IRC8MEN Internal High Speed oscillator Enable 0 1 read-write IRC8MENread-writeOffClock Off0OnClock On1 IRC8MSTB IRC8M High Speed Internal Oscillator stabilization Flag 1 1 read-only IRC8MSTBRreadNotReadyIRC8M is not stable0ReadyIRC8M is stable1 IRC8MADJ High Speed Internal Oscillator clock trim adjust value 3 5 read-write 031 IRC8MCALIB High Speed Internal Oscillator calibration value register 8 8 read-only 0255 HXTALEN External High Speed oscillator Enable 16 1 read-write HXTALSTB External crystal oscillator (HXTAL) clock stabilization flag 17 1 read-only HXTALSTBRreadNotReadyHXTAL is not stable0ReadyHXTAL is stable1 HXTALBPS External crystal oscillator (HXTAL) clock bypass mode enable 18 1 read-write HXTALBPSread-writeNotBypassedHXTAL crystal oscillator not bypassed0BypassedHXTAL crystal oscillator bypassed with external clock1 CKMEN HXTAL Clock Monitor Enable 19 1 read-write CKMENread-writeOffClock monitor disabled0OnClock monitor enabled1 PLLEN PLL enable 24 1 read-write PLLSTB PLL Clock Stabilization Flag 25 1 read-only PLLSTBRreadNotReadyPLL is not stable0ReadyPLL is stable1 CFG0 CFG0 Clock configuration register 0 (RCU_CFG0) 0x04 0x20 0x00000000 SCS System clock switch 0 2 read-write SCSread-writeIRC8MIRC8M used as system clock0HXTALHXTAL used as system clock1PLLPLL used as system clock2 SCSS System clock switch status 2 2 read-only SCSSread-writeIRC8MIRC8M used as system clock0HXTALHXTAL used as system clock1PLLPLL used as system clock2 AHBPSC AHB prescaler selection 4 4 read-write AHBPSCread-writeDiv1CK_SYS0Div2CK_SYS divided by 28Div4CK_SYS divided by 49Div8CK_SYS divided by 810Div16CK_SYS divided by 1611Div64CK_SYS divided by 6412Div128CK_SYS divided by 12813Div256CK_SYS divided by 25614Div512CK_SYS divided by 51215 APB1PSC APB1 prescaler selection 8 3 read-write APB1PSCread-writeDiv1CK_AHB0Div2CK_AHB divided by 24Div4CK_AHB divided by 45Div8CK_AHB divided by 86Div16CK_AHB divided by 167 APB2PSC APB2 prescaler selection 11 3 read-write ADCPSC ADC clock prescaler selection 14 2 read-write ADCPSCread-writeDiv2CK_APB2 divided by 20Div4CK_APB2 divided by 41Div6CK_APB2 divided by 62Div8CK_APB2 divided by 83 PLLSEL PLL Clock Source Selection 16 1 read-write PLLSELread-writeIRC8M_2IRC8M / 2 selected as PLL source clock0HXTALHXTAL selected as PLL source clock1 PLLPREDV HXTAL divider for PLL source clock selection. 17 1 read-write PLLPREDVread-writeDiv1HXTAL clock not divided0Div2HXTAL clock divided by 21 PLLMF PLL multiply factor 18 4 read-write PLLMFread-writeMul2PLL input clock x20Mul3PLL input clock x31Mul4PLL input clock x42Mul5PLL input clock x53Mul6PLL input clock x64Mul7PLL input clock x75Mul8PLL input clock x86Mul9PLL input clock x97Mul10PLL input clock x108Mul11PLL input clock x119Mul12PLL input clock x1210Mul13PLL input clock x1311Mul14PLL input clock x1412Mul15PLL input clock x1513Mul16PLL input clock x1614Mul16xPLL input clock x1615 USBDPSC USBD clock prescaler selection 22 2 read-write USBDPSCread-writeDIV1_5PLL clock is divided by 1.50DIV1PLL clock is not divided1DIV2_5PLL clock is divided by 2.52DIV2PLL clock is divided by 23 CKOUTSEL CK_OUT Clock Source Selection 24 3 read-write CKOUTSELread-writeNoneNo clock selected0IRC14MInternal 14 MHz RC oscillator clock selected1LSI40KInternal 40 kHz RC oscillator clock selected2LXTALExternal low speed oscillator clock selected3SYSCLKSystem clock selected4IRC8MInternal RC 8 MHz (HSI) oscillator clock selected5HXTALExternal 4-32 MHz (HSE) oscillator clock selected6PLLPLL clock selected (divided by 1 or 2, depending on PLLDV)7 PLLMF_MSB Bit 4 of PLLMF register 27 1 read-write PLLMF_MSBread-writeNoneValue of PLLMF is as set0Plus15Add 15 to the value of PLLMF1 CKOUTDIV The CK_OUT divider which the CK_OUT frequency can be reduced 28 3 read-write CKOUTDIVread-writeDiv1CK_OUT is divided by 10Div2CK_OUT is divided by 21Div4CK_OUT is divided by 42Div8CK_OUT is divided by 83Div16CK_OUT is divided by 164Div32CK_OUT is divided by 325Div64CK_OUT is divided by 646Div128CK_OUT is divided by 1287 PLLDV The CK_PLL divide by 1 or 2 for CK_OUT 31 1 read-write PLLDVread-writeDiv2PLL is divided by 2 for CK_OUT0Div1PLL is not divided for CK_OUT1 INT INT Clock interrupt register (RCU_INT) 0x08 0x20 0x00000000 IRC40KSTBIF IRC40K stabilization interrupt flag 0 1 read-only IRC40KSTBIFRreadNotInterruptedNo interrupt generated0InterruptedIRC40K stabilisation interrupt generated1 LXTALSTBIF LXTAL stabilization interrupt flag 1 1 read-only LXTALSTBIFRreadNotInterruptedNo interrupt generated0InterruptedLXTAL stabilisation interrupt generated1 IRC8MSTBIF IRC8M stabilization interrupt flag 2 1 read-only IRC8MSTBIFRreadNotInterruptedNo interrupt generated0InterruptedIRC8M stabilisation interrupt generated1 HXTALSTBIF HXTAL stabilization interrupt flag 3 1 read-only HXTALSTBIFRreadNotInterruptedNo interrupt generated0InterruptedHXTAL stabilisation interrupt generated1 PLLSTBIF PLL stabilization interrupt flag 4 1 read-only PLLSTBIFRreadNotInterruptedNo interrupt generated0InterruptedPLL stabilisation interrupt generated1 IRC14MSTBIF IRC14M stabilization interrupt flag 5 1 read-only IRC14MSTBIFRreadNotInterruptedNo interrupt generated0InterruptedIRC14M stabilisation interrupt generated1 CKMIF HXTAL Clock Stuck Interrupt Flag 7 1 read-only CKMIFRreadNotInterruptedClock operating normally0InterruptedHXTAL clock stuck1 IRC40KSTBIE IRC40K Stabilization interrupt enable 8 1 read-write IRC40KSTBIEread-writeDisabledInterrupt disabled0EnabledInterrupt enabled1 LXTALSTBIE LXTAL Stabilization Interrupt Enable 9 1 read-write LXTALSTBIEread-writeDisabledInterrupt disabled0EnabledInterrupt enabled1 IRC8MSTBIE IRC8M Stabilization Interrupt Enable 10 1 read-write IRC8MSTBIEread-writeDisabledInterrupt disabled0EnabledInterrupt enabled1 HXTALSTBIE HXTAL Stabilization Interrupt Enable 11 1 read-write HXTALSTBIEread-writeDisabledInterrupt disabled0EnabledInterrupt enabled1 PLLSTBIE PLL Stabilization Interrupt Enable 12 1 read-write PLLSTBIEread-writeDisabledInterrupt disabled0EnabledInterrupt enabled1 IRC14MSTBIE IRC14M Stabilization Interrupt Enable 13 1 read-write IRC14MSTBIEread-writeDisabledInterrupt disabled0EnabledInterrupt enabled1 IRC40KSTBIC IRC40K Stabilization Interrupt Clear 16 1 write-only IRC40KSTBICWwriteClearClear IRC40KSTBIF flag1 LXTALSTBIC LXTAL Stabilization Interrupt Clear 17 1 write-only LXTALSTBICWwriteClearClear LXTALSTBIF flag1 IRC8MSTBIC IRC8M Stabilization Interrupt Clear 18 1 write-only IRC8MSTBICWwriteClearClear IRC8MSTBIF flag1 HXTALSTBIC HXTAL Stabilization Interrupt Clear 19 1 write-only HXTALSTBICWwriteClearClear HXTALSTBIF flag1 PLLSTBIC PLL stabilization Interrupt Clear 20 1 write-only PLLSTBICWwriteClearClear PLLSTBIF flag1 IRC14MSTBIC IRC14M stabilization Interrupt Clear 21 1 write-only IRC14MSTBICWwriteClearClear IRC14MSTBIF flag1 CKMIC HXTAL Clock Stuck Interrupt Clear 23 1 write-only CKMICWwriteClearClear CKMIF flag1 APB2RST APB2RST APB2 reset register (RCU_APB2RST) 0x0C 0x20 read-write 0x00000000 CFGRST System configuration reset 0 1 CFGRSTread-writeResetReset the selected module1 ADCRST ADC reset 9 1 TIMER0RST TIMER0 reset 11 1 SPI0RST SPI0 Reset 12 1 USART0RST USART0 Reset 14 1 TIMER14RST TIMER14 reset 16 1 TIMER15RST TIMER15 reset 17 1 TIMER16RST TIMER16 reset 18 1 APB1RST APB1RST APB1 reset register (RCU_APB1RST) 0x10 0x20 read-write 0x00000000 TIMER1RST TIMER1 timer reset 0 1 TIMER1RSTread-writeResetReset the selected module1 TIMER2RST TIMER2 timer reset 1 1 TIMER5RST TIMER5 timer reset 4 1 TIMER13RST TIMER13 timer reset 8 1 WWDGTRST Window watchdog timer reset 11 1 SPI1RST SPI1 reset 14 1 SPI2RST SPI2 reset 15 1 USART1RST USART1 reset 17 1 I2C0RST I2C0 reset 21 1 I2C1RST I2C1 reset 22 1 USBDRST USBD reset 23 1 PMURST Power control reset 28 1 DACRST DAC reset 29 1 CECRST HDMI CEC reset 30 1 AHBEN AHBEN AHB enable register (RCU_AHBEN) 0x14 0x20 read-write 0x00000014 DMAEN DMA clock enable 0 1 DMAENread-writeDisabledThe selected clock is disabled0EnabledThe selected clock is enabled1 SRAMEN SRAM interface clock enable 2 1 FMCEN FMC clock enable 4 1 CRCEN CRC clock enable 6 1 PAEN GPIO port A clock enable 17 1 PBEN GPIO port B clock enable 18 1 PCEN GPIO port C clock enable 19 1 PDEN GPIO port D clock enable 20 1 PFEN GPIO port F clock enable 22 1 TSIEN TSI clock enable 24 1 APB2EN APB2EN APB2 enable register (RCU_APB2EN) 0x18 0x20 read-write 0x00000000 CFGCMPEN System configuration and comparator clock enable 0 1 CFGCMPENread-writeDisabledThe selected clock is disabled0EnabledThe selected clock is enabled1 ADCEN ADC interface clock enable 9 1 TIMER0EN TIMER0 timer clock enable 11 1 SPI0EN SPI0 clock enable 12 1 USART0EN USART0 clock enable 14 1 TIMER14EN TIMER14 timer clock enable 16 1 TIMER15EN TIMER15 timer clock enable 17 1 TIMER16EN TIMER16 timer clock enable 18 1 APB1EN APB1EN APB1 enable register (RCU_APB1EN) 0x1C 0x20 read-write 0x00000000 TIMER1EN TIMER1 timer clock enable 0 1 TIMER1ENread-writeDisabledThe selected clock is disabled0EnabledThe selected clock is enabled1 TIMER2EN TIMER2 timer clock enable 1 1 TIMER5EN TIMER5 timer clock enable 4 1 TIMER13EN TIMER13 timer clock enable 8 1 WWDGTEN Window watchdog timer clock enable 11 1 SPI1EN SPI1 clock enable 14 1 SPI2EN SPI2 clock enable 15 1 USART1EN USART1 clock enable 17 1 I2C0EN I2C0 clock enable 21 1 I2C1EN I2C1 clock enable 22 1 USBDEN USBD clock enable 23 1 PMUEN Power interface clock enable 28 1 DACEN DAC interface clock enable 29 1 CECEN HDMI CEC interface clock enable 30 1 BDCTL BDCTL Backup domain control register (RCU_BDCTL) 0x20 0x20 0x00000018 LXTALEN LXTAL enable 0 1 read-write LXTALENread-writeOffLXTAL oscillator Off0OnLXTAL oscillator On1 LXTALSTB External low-speed oscillator stabilization 1 1 read-only LXTALSTBRreadNotReadyLXTAL oscillator not ready0ReadyLXTAL oscillator ready1 LXTALBPS LXTAL bypass mode enable 2 1 read-write LXTALBPSread-writeNotBypassedLXTAL crystal oscillator not bypassed0BypassedLXTAL crystal oscillator bypassed with external clock1 LXTALDRI LXTAL drive capability 3 2 read-write LXTALDRIread-writeLowLow driving capability0MediumLowMedium low driving capability1MediumHighMedium high driving capability2HighHigh driving capability (reset value)3 RTCSRC RTC clock entry selection 8 2 read-write RTCSRCread-writeNoClockNo clock0LXTALLXTAL oscillator clock used as RTC clock1IRC40KIRC40K oscillator clock used as RTC clock2HXTALHXTAL oscillator / 32 used as RTC clock3 RTCEN RTC clock enable 15 1 read-write RTCENread-writeDisabledRTC clock disabled0EnabledRTC clock enabled1 BKPRST Backup domain reset 16 1 read-write BKPRSTread-writeNoResetReset not activated0ResetReset the entire RTC domain1 RSTSCK RSTSCK Reset source /clock register (RCU_RSTSCK) 0x24 0x20 0x0C000000 IRC40KEN IRC40K enable 0 1 read-write IRC40KENread-writeOffIRC40K oscillator disabled0OnIRC40K oscillator enabled1 IRC40KSTB IRC40K stabilization 1 1 read-only IRC40KSTBRreadNotReadyIRC40K oscillator is not stable0ReadyIRC40K oscillator is stable1 V12RSTF V12 domain Power reset flag 23 1 read-write V12RSTFRreadNoResetNo reset has occured0ResetA reset has occured1 RSTFC Reset flag clear 24 1 read-write RSTFCWwriteClearClears reset flags1 OBLRSTF Option byte loader reset flag 25 1 read-write EPRSTF External PIN reset flag 26 1 read-write PORRSTF Power reset flag 27 1 read-write SWRSTF Software reset flag 28 1 read-write FWDGTRSTF Free Watchdog timer reset flag 29 1 read-write WWDGTRSTF Window watchdog timer reset flag 30 1 read-write LPRSTF Low-power reset flag 31 1 read-write AHBRST AHBRST AHB reset register 0x28 0x20 read-write 0x00000000 PARST GPIO port A reset 17 1 PARSTread-writeResetReset the selected module1 PBRST GPIO port B reset 18 1 PCRST GPIO port C reset 19 1 PDRST GPIO port D reset 20 1 PFRST GPIO port F reset 22 1 TSIRST TSI unit reset 24 1 CFG1 CFG1 Configuration register 1 0x2C 0x20 read-write 0x00000000 HXTALPREDV CK_HXTAL divider previous PLL 0 4 HXTALPREDVread-writeDiv1HXTAL input to PLL not divided0Div2HXTAL input to PLL divided by 21Div3HXTAL input to PLL divided by 32Div4HXTAL input to PLL divided by 43Div5HXTAL input to PLL divided by 54Div6HXTAL input to PLL divided by 65Div7HXTAL input to PLL divided by 76Div8HXTAL input to PLL divided by 87Div9HXTAL input to PLL divided by 98Div10HXTAL input to PLL divided by 109Div11HXTAL input to PLL divided by 1110Div12HXTAL input to PLL divided by 1211Div13HXTAL input to PLL divided by 1312Div14HXTAL input to PLL divided by 1413Div15HXTAL input to PLL divided by 1514Div16HXTAL input to PLL divided by 1615 CFG2 CFG2 Configuration register 2 0x30 0x20 read-write 0x00000000 USART0SEL CK_USART0 clock source selection 0 2 USART0SELread-writeAPB2APB2 selected as USART0 clock source0SYSSYS selected as USART0 clock source1LXTALLXTAL selected as USART0 clock source2IRC8MIRC8M selected as USART0 clock source3 CECSEL CK_CEC clock source selection 6 1 CECSELread-writeIRC8M_Div244IRC8M clock divided by 244 selected as CEC clock source0LXTALLXTAL clock selected as CEC clock source1 ADCSEL CK_ADC clock source selection 8 1 ADCSELread-writeIRC14MIRC14M selected as ADC clock source0APB2APB2 divided by prescaler selected as ADC clock source1 CTL1 CTL1 Control register 1 0x34 0x20 0x00000080 IRC14MEN IRC14M Internal 14M RC oscillator Enable 0 1 read-write IRC14MENread-writeOffClock Off0OnClock On1 IRC14MSTB IRC14M Internal 14M RC Oscillator stabilization Flag 1 1 read-only IRC14MSTBRreadNotReadyIRC14M is not stable0ReadyIRC14M is stable1 IRC14MADJ Internal 14M RC Oscillator clock trim adjust value 3 5 read-write 031 IRC14MCALIB Internal 14M RC Oscillator calibration value register 8 8 read-only 0255 ADDEN ADDEN Additional enable register 0xF8 0x20 0x00000000 I2C2EN I2C2 unit clock enable 0 1 read-write I2C2ENread-writeDisabledThe selected clock is disabled0EnabledThe selected clock is enabled1 ADDRST ADDRST Additional reset register 0xFC 0x20 0x00000000 I2C2RST I2C2 unit reset 0 1 read-write I2C2RSTread-writeResetReset the selected module1 VKEY VKEY Voltage key register 0x100 0x20 0x00000000 KEY The key of RCU_PDVSEL and RCU_DSV register 0 32 read-write KEYWwriteEnableAllow PDVSEL and DSV to be written439041101 DSV DSV Deep-sleep mode voltage register 0x134 0x20 0x00000000 DSLPVS Deep-sleep mode voltage select 0 3 read-write DSLPVSread-writeV1_2The core voltage is 1.2 V in deep-sleep mode0V1_1The core voltage is 1.1 V in deep-sleep mode1V1_0The core voltage is 1.0 V in deep-sleep mode2V0_9The core voltage is 0.9 V in deep-sleep mode3 PDVSEL PDVSEL Power down voltage select register 0x138 0x20 0x00000000 PDRVS Power down voltage select 0 1 read-write PDRVSread-writeV2_6The power down voltage is 2.6 V0V1_8The power down voltage is 1.8 V1 RTC Real-time clock RTC 0x40002800 0x0 0x400 registers RTC 2 TIME TIME Time of day register 0x0 0x20 read-write 0x00000000 PM AM/PM mark 22 1 HRT Hour tens in BCD format 20 2 HRU Hour units in BCD format 16 4 MNT Minute tens in BCD format 12 3 MNU Minute units in BCD format 8 4 SCT Second tens in BCD format 4 3 SCU Second units in BCD format 0 4 DATE DATE date register 0x4 0x20 read-write 0x00002101 YRT Year tens in BCD format 20 4 YRU Year units in BCD format 16 4 DOW Week day units 13 3 MONT Month tens in BCD format 12 1 MONU Month units in BCD format 8 4 DAYT Date tens in BCD format 4 2 DAYU Date units in BCD format 0 4 CTL CTL control register 0x8 0x20 0x00000000 TSEG Valid event edge of time-stamp 3 1 read-write REFEN Reference clock detection function enable 4 1 read-write BPSHAD Shadow registers bypass control 5 1 read-write CS Clock System 6 1 read-write ALRM0EN Alarm-0 function enable 8 1 read-write TSEN time-stamp function enable 11 1 read-write ALRM0IE RTC alarm-0 interrupt enable 12 1 read-write TSIE Time-stamp interrupt enable 15 1 read-write A1H Add 1 hour(summer time change 16 1 write-only S1H Subtract 1 hour(winter time change) 17 1 write-only DSM Daylight saving mark 18 1 read-write COS Calibration output selection 19 1 read-write OPOL Output polarity 20 1 read-write OS Output selection 21 2 read-write COEN Calibration output enable 23 1 read-write STAT STAT Status register 0xC 0x20 0x00000007 ALRM0WF Alarm 0 configuration can be write flag 0 1 read-only SOPF Shift function operation pending flag 3 1 read-write YCM Year configuration mark 4 1 read-only RSYNF Register synchronization flag 5 1 read-write INITF Initialization state flag 6 1 read-only INITM enter initialization mode 7 1 read-write ALRM0F Alarm-0 occurs flag 8 1 read-write TSF Time-stamp flag 11 1 read-write TSOVRF Time-stamp overflow flag 12 1 read-write TP0F RTC_TAMP0 detected flag 13 1 read-write TP1F RTC_TAMP1 detected flag 14 1 read-write SCPF Smooth calibration pending flag 16 1 read-only PSC PSC Time prescaler register 0x10 0x20 read-write 0x007F00FF FACTOR_A Asynchronous prescaler factor 16 7 FACTOR_S Synchronous prescaler factor 0 15 ALRM0TD ALRM0TD Alarm 0 Time and date register 0x1C 0x20 read-write 0x00000000 MSKD Alarm date mask bit 31 1 DOWS Day of the week selected 30 1 DAYT Date tens in BCD code 28 2 DAYU Date units or week day in BCD code 24 4 MSKH Alarm hour mask bit 23 1 PM AM/PM flag 22 1 HRT Hour tens in BCD code 20 2 HRU Hour units in BCD code 16 4 MSKM Alarm minutes mask bit 15 1 MNT Minutes tens in BCD code 12 3 MNU Minutes units in BCD code 8 4 MSKS Alarm second mask bit 7 1 SCT Second tens in BCD code 4 3 SCU Second units in BCD code 0 4 WPK WPK Write protection key register 0x24 0x20 write-only 0x00000000 WPK Write protection key 0 8 SS SS sub second register 0x28 0x20 read-only 0x00000000 SSC Sub second value 0 16 SHIFTCTL SHIFTCTL Shift function control register 0x2C 0x20 write-only 0x00000000 A1S One second add 31 1 SFS Subtract a fraction of a second 0 15 TTS TTS Time of time stamp register 0x30 0x20 read-only 0x00000000 PM AM/PM mark 22 1 HRT Hour tens in BCD code 20 2 HRU Hour units in BCD code 16 4 MNT Minute tens in BCD code 12 3 MNU Minute units in BCD code 8 4 SCT Second tens in BCD code 4 3 SCU Second units in BCD code 0 4 DTS DTS Date of time stamp register 0x34 0x20 read-only 0x00000000 DOW Week day units 13 3 MONT Month tens in BCD code 12 1 MONU Month units in BCD code 8 4 DAYT Date tens in BCD code 4 2 DAYU Date units in BCD code 0 4 SSTS SSTS Sub second of time stamp register 0x38 0x20 read-only 0x00000000 SSC Sub second value 0 16 HRFC HRFC High resolution frequency compensation register 0x3C 0x20 read-write 0x00000000 FREQI Increase RTC frequency by 488.5ppm 15 1 CWND8 Frequency compensation window 8 second selected 14 1 CWND16 Frequency compensation window 16 second selected 13 1 CMSK Calibration mask number 0 9 TAMP TAMP Tamper register 0x40 0x20 read-write 0x00000000 PC15MDE PC15 mode 23 1 PC15VAL PC15 value 22 1 PC14MDE PC14 mode 21 1 PC14VAL PC14 value 20 1 PC13MDE PC13 mode 19 1 PC13VAL Alarm output type control/PC13 output value 18 1 DISPU RTC_TAMPx pull up disable bit 15 1 PRCH Precharge duration time of RTC_TAMPx 13 2 FLT RTC_TAMPx filter count setting 11 2 FREQ Sample frequency of tamper event detection 8 3 TPTS Make tamper function used for timestamp function 7 1 TP1EG Tamper 1 event trigger edge for RTC_TAMP1 input 4 1 TP1EN Tamper 1 detection enable 3 1 TPIE Tamper detection interrupt enable 2 1 TP0EG Tamper 0 event trigger edge for RTC_TAMP0 input 1 1 TP0EN RTC_TAMP1 input detection enable 0 1 ALRM0SS ALRM0SS Alarm 0 sub second register 0x44 0x20 read-write 0x00000000 MSKSSC Mask control bit of SSC 24 4 SSC Alarm sub second value 0 15 BKP0 BKP0 backup register 0x50 0x20 read-write 0x00000000 DATA Backup domain registers 0 32 BKP1 BKP1 backup register 0x54 0x20 read-write 0x00000000 DATA Backup domain registers 0 32 BKP2 BKP2 backup register 0x58 0x20 read-write 0x00000000 DATA Backup domain registers 0 32 BKP3 BKP3 backup register 0x5C 0x20 read-write 0x00000000 DATA Backup domain registers 0 32 BKP4 BKP4 backup register 0x60 0x20 read-write 0x00000000 DATA Backup domain registers 0 32 SPI0 Serial peripheral interface SPI 0x40013000 0x0 0x400 registers SPI0 25 CTL0 CTL0 control register 0 0x0 0x10 read-write 0x0000 BDEN Bidirectional enable 15 1 BDENread-writeUnidirectional2-line unidirectional data mode selected0Bidirectional1-line bidirectional data mode selected1 BDOEN Bidirectional Transmit output enable 14 1 BDOENread-writeReceiveOnlyReceive-only mode0TransmitOnlyTransmit-only mode1 CRCEN Hardware CRC calculation enable 13 1 CRCENread-writeDisabledCRC calculation disabled0EnabledCRC calculation enabled1 CRCNT CRC transfer next 12 1 CRCNTread-writeDataNext transmit value is data from Tx buffer0CRCNext transmit value is CRC value from TCRC1 FF16 Data frame format 11 1 FF16read-writeEightBit8-bit data frame format is selected for transmission/reception0SixteenBit16-bit data frame format is selected for transmission/reception1 RO Receive only 10 1 ROread-writeFullDuplexFull duplex (Transmit and receive)0ReceiveOnlyOutput disabled (Receive-only mode)1 SWNSSEN NSS Software Mode Selection 9 1 SWNSSENread-writeHardwareSoftware slave management disabled0SoftwareSoftware slave management enabled1 SWNSS NSS Pin Selection In NSS Software Mode 8 1 SWNSSread-writeSlaveSelectedNSS is pulled low0SlaveNotSelectedNSS is pulled high1 LF LSB First Mode 7 1 LFread-writeMSBFirstData is transmitted/received with the MSB first0LSBFirstData is transmitted/received with the LSB first1 SPIEN SPI enable 6 1 SPIENread-writeDisabledPeripheral disabled0EnabledPeripheral enabled1 PSC Master Clock Prescaler Selection 3 3 PSCread-writeDiv2PCLK / 20Div4PCLK / 41Div8PCLK / 82Div16PCLK / 163Div32PCLK / 324Div64PCLK / 645Div128PCLK / 1286Div256PCLK / 2567 MSTMOD Master selection 2 1 MSTMODread-writeSlaveSlave configuration0MasterMaster configuration1 CKPL Clock Polarity Selection 1 1 CKPLread-writeIdleLowCLK pulled low when idle0IdleHighCLK pulled high when idle1 CKPH Clock Phase Selection 0 1 CKPHread-writeFirstEdgeThe first clock transition is the first data capture edge0SecondEdgeThe second clock transition is the first data capture edge1 CTL1 CTL1 control register 1 0x04 0x10 read-write 0x0000 TBEIE Tx buffer empty interrupt enable 7 1 TBEIEread-writeDisabledTBE interrupt disabled0EnabledTBE interrupt enabled1 RBNEIE RX buffer not empty interrupt enable 6 1 RBNEIEread-writeDisabledRBNE interrupt disabled0EnabledRBNE interrupt enabled1 ERRIE Error interrupt enable 5 1 ERRIEread-writeDisabledError interrupt disabled0EnabledError interrupt enabled1 NSSDRV Drive NSS Output 2 1 NSSDRVread-writeDisabledNSS output is disabled in master mode0EnabledNSS output is enabled in master mode1 DMATEN Transmit Buffer DMA Enable 1 1 DMATENread-writeDisabledTx buffer DMA disabled0EnabledTx buffer DMA enabled1 DMAREN Receive Buffer DMA Enable 0 1 DMARENread-writeDisabledRx buffer DMA disabled0EnabledRx buffer DMA enabled1 STAT STAT status register 0x08 0x10 0x0002 TRANS Transmitting On-going Bit 7 1 read-only TRANSread-writeIdleSPI or I2S is idle0BusySPI or I2S is currently transmitting or receiving1 RXORERR Reception Overrun Error Bit 6 1 read-only RXORERRread-writeNoOverrunNo overrun occurred0OverrunOverrun occurred1 CONFERR SPI Configuration error 5 1 read-only CONFERRread-writeNoFaultNo configuration fault occurred0FaultConfiguration fault occurred1 CRCERR SPI CRC Error Bit 4 1 read-write CRCERRRreadMatchCRC value received matches the SPIx_RXCRCR value0NoMatchCRC value received does not match the SPIx_RXCRCR value1 CRCERRWwriteClearClear CRC error0 TXURERR Transmission underrun error bit 3 1 read-only TXURERRread-writeNoUnderrunNo underrun occurred0UnderrunUnderrun occurred1 I2SCH I2S channel side 2 1 read-only I2SCHread-writeLeftChannel left has to be transmitted or has been received0RightChannel right has to be transmitted or has been received1 TBE Transmit Buffer Empty 1 1 read-only TBEread-writeNotEmptyTx buffer not empty0EmptyTx buffer empty1 RBNE Receive Buffer Not Empty 0 1 read-only RBNEread-writeEmptyRx buffer empty0NotEmptyRx buffer not empty1 DATA DATA data register 0x0C 0x10 read-write 0x0000 DATA Data register 0 16 065535 CRCPOLY CRCPOLY CRC polynomial register 0x10 0x10 read-write 0x0007 CRCPOLY CRC polynomial register 0 16 065535 RCRC RCRC Receive CRC register 0x14 0x10 read-only 0x0000 RCRC CRC value of the received bytes 0 16 065535 TCRC TCRC Transmit CRC register 0x18 0x10 read-only 0x0000 TCRC CRC value of the transmitted bytes 0 16 065535 I2SCTL I2SCTL I2S control register 0x1C 0x10 read-write 0x0000 I2SSEL I2S mode selection 11 1 I2SSELread-writeSPIModeSPI mode is selected0I2SModeI2S mode is selected1 I2SEN I2S Enable 10 1 I2SENread-writeDisabledI2S peripheral is disabled0EnabledI2S peripheral is enabled1 I2SOPMOD I2S configuration mode 8 2 I2SOPMODread-writeSlaveTxSlave - transmit0SlaveRxSlave - receive1MasterTxMaster - transmit2MasterRxMaster - receive3 PCMSMOD PCM frame synchronization mode 7 1 PCMSMODread-writeShortShort frame synchronisation0LongLong frame synchronisation1 I2SSTD I2S standard selection 4 2 I2SSTDread-writePhilipsI2S Philips standard0MSBMSB justified standard1LSBLSB justified standard2PCMPCM standard3 CKPL Idle state clock polarity 3 1 CKPLread-writeIdleLowI2S clock inactive state is low level0IdleHighI2S clock inactive state is high level1 DTLEN Data length 1 2 DTLENread-writeSixteenBit16-bit data length0TwentyFourBit24-bit data length1ThirtyTwoBit32-bit data length2 CHLEN Channel length 0 1 CHLENread-writeSixteenBit16-bit wide0ThirtyTwoBit32-bit wide1 I2SPSC I2SPSC I2S prescaler register 0x20 0x10 read-write 0002 MCKOEN I2S_MCK output enable 9 1 MCKOENread-writeDisabledMaster clock output is disabled0EnabledMaster clock output is enabled1 OF Odd factor for the prescaler 8 1 OFread-writeEvenReal divider value is DIV * 20OddReal divider value is (DIV * 2) + 11 DIV Dividing factor for the prescaler 0 8 1255 SPI1 0x40003800 SPI1 26 SPI2 0x40003C00 SPI2 51 SYSCFG System configuration controller SYSCFG 0x40010000 0x0 0x001C registers CFG0 CFG0 System configuration register 0 0x0 0x20 read-write 0x00000000 PB9_HCCE PB9 pin high current capability enable 19 1 PB9_HCCEread-writeLowCurrentHigh current capability is disabled0HighCurrentHigh current capability is enabled, and speed control is bypassed1 TIMER16_DMA_RMP Timer 16 DMA request remapping enable 12 1 TIMER16_DMA_RMPread-writeChannel0Timer 16 DMA requests are mapped to DMA channel 00Channel1Timer 16 DMA requests are remapped to DMA channel 11 TIMER15_DMA_RMP Timer 15 DMA request remapping enable 11 1 TIMER15_DMA_RMPread-writeChannel2Timer 15 DMA requests are mapped to DMA channel 20Channel3Timer 15 DMA requests are remapped to DMA channel 31 USART0_RX_DMA_RMP USART0_RX DMA request remapping enable 10 1 USART0_RX_DMA_RMPread-writeChannel2USART0 RX DMA requests are mapped to DMA channel 20Channel4USART0 RX DMA requests are remapped to DMA channel 41 USART0_TX_DMA_RMP USART0_TX DMA request remapping enable 9 1 USART0_TX_DMA_RMPread-writeChannel1USART0 TX DMA requests are mapped to DMA channel 10Channel3USART0 TX DMA requests are remapped to DMA channel 31 ADC_DMA_RMP ADC DMA request remapping enable 8 1 ADC_DMA_RMPread-writeChannel0ADC DMA requests are mapped to DMA channel 00Channel1ADC DMA requests are remapped to DMA channel 11 BOOT_MODE Boot mode 0 2 read-only BOOT_MODEread-writeFlashBoot from main flash0SystemMemoryBoot from system memory1SRAMBoot from embedded SRAM3 CFG1 CFG1 System configuration register 1 0x04 0x20 read-write 0x00000000 SLCD_DECA Decoupling capacitance connection for SLCD 1 3 07 EXTISS0 EXTISS0 EXTI sources selection register 0 0x8 0x20 read-write 0x00000000 EXTI3_SS EXTI 3 sources selection 12 4 EXTI3_SSread-writePA3PA3 pin0PB3PB3 pin1PC3PC3 pin2 EXTI2_SS EXTI 2 sources selection 8 4 EXTI2_SSread-writePA2PA2 pin0PB2PB2 pin1PC2PC2 pin2PD2PD2 pin3 EXTI1_SS EXTI 1 sources selection 4 4 EXTI1_SSread-writePA1PA1 pin0PB1PB1 pin1PC1PC1 pin2PF1PF1 pin5 EXTI0_SS EXTI 0 sources selection 0 4 EXTI0_SSread-writePA0PA0 pin0PB0PB0 pin1PC0PC0 pin2PF0PF0 pin5 EXTISS1 EXTISS1 EXTI sources selection register 1 0xC 0x20 read-write 0x00000000 EXTI7_SS EXTI 7 sources selection 12 4 EXTI7_SSread-writePA7PA7 pin0PB7PB7 pin1PC7PC7 pin2PF7PF7 pin5 EXTI6_SS EXTI 6 sources selection 8 4 EXTI6_SSread-writePA6PA6 pin0PB6PB6 pin1PC6PC6 pin2PF6PF6 pin5 EXTI5_SS EXTI 5 sources selection 4 4 EXTI5_SSread-writePA5PA5 pin0PB5PB5 pin1PC5PC5 pin2PF5PF5 pin5 EXTI4_SS EXTI 4 sources selection 0 4 EXTI4_SSread-writePA4PA4 pin0PB4PB4 pin1PC4PC4 pin2PF4PF4 pin5 EXTISS2 EXTISS2 EXTI sources selection register 2 0x10 0x20 read-write 0x00000000 EXTI11_SS EXTI 11 sources selection 12 4 EXTI11_SSread-writePA11PA11 pin0PB11PB11 pin1PC11PC11 pin2 EXTI10_SS EXTI 10 sources selection 8 4 EXTI10_SSread-writePA10PA10 pin0PB10PB10 pin1PC10PC10 pin2 EXTI9_SS EXTI 9 sources selection 4 4 EXTI9_SSread-writePA9PA9 pin0PB9PB9 pin1PC9PC9 pin2 EXTI8_SS EXTI 8 sources selection 0 4 EXTI8_SSread-writePA8PA8 pin0PB8PB8 pin1PC8PC8 pin2 EXTISS3 EXTISS3 EXTI sources selection register 3 0x14 0x20 read-write 0x00000000 EXTI15_SS EXTI 15 sources selection 12 4 EXTI15_SSread-writePA15PA15 pin0PB15PB15 pin1PC15PC15 pin2 EXTI14_SS EXTI 14 sources selection 8 4 EXTI14_SSread-writePA14PA14 pin0PB14PB14 pin1PC14PC14 pin2 EXTI13_SS EXTI 13 sources selection 4 4 EXTI13_SSread-writePA13PA13 pin0PB13PB13 pin1PC13PC13 pin2 EXTI12_SS EXTI 12 sources selection 0 4 EXTI12_SSread-writePA12PA12 pin0PB12PB12 pin1PC12PC12 pin2 CFG2 CFG2 System configuration register 2 0x18 0x20 read-write 0x00000000 SRAM_PCEF SRAM parity check error flag 8 1 SRAM_PCEFRreadNoErrorNo SRAM parity check error detected0ErrorSRAM parity check error detected1 SRAM_PCEFWwriteClearClear error flag1 LVD_LOCK LVD lock 2 1 LVD_LOCKread-writeUnlockedThe LVD interrupt is disconnected from the break input0LockedThe LVD interrupt is connected to the break input1 SRAM_PARITY_ERROR_LOCK SRAM parity check error lock 1 1 SRAM_PARITY_ERROR_LOCKread-writeUnlockedThe SRAM parity check error is disconnected from the break input0LockedThe SRAM parity check error is connected to the break input1 LOCKUP_LOCK Cortex-M3 LOCKUP output lock 0 1 LOCKUP_LOCKread-writeUnlockedThe Cortex-M3 LOCKUP output is disconnected from the break input0LockedThe Cortex-M3 LOCKUP output is connected to the break input1 TIMER0 Advanced-timers TIMER 0x40012C00 0x0 0x400 registers TIMER0_BRK_UP_TRG_COM 13 TIMER0_CC 14 CTL0 CTL0 control register 0 0x0 0x10 read-write 0x0000 CKDIV Clock division 8 2 CKDIVread-writeDiv1t_DTS = t_CK_INT0Div2t_DTS = 2 × t_CK_INT1Div4t_DTS = 4 × t_CK_INT2 ARSE Auto-reload shadow enable 7 1 ARSEread-writeDisabledThe shadow register for CAR is disabled0EnabledThe shadow register for CAR is enabled1 CAM Counter aligns mode selection 5 2 CAMread-writeEdgeAlignedThe counter counts up or down depending on the direction bit0CenterAlignedCountingDownThe counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down.1CenterAlignedCountingUpThe counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up.2CenterAlignedCountingUpDownThe counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down.3 DIR Direction 4 1 DIRread-writeUpCounter used as upcounter0DownCounter used as downcounter1 SPM Single pulse mode 3 1 SPMread-writeDisabledCounter is not stopped at update event0EnabledCounter stops counting at the next update event (clearing the CEN bit)1 UPS Update source 2 1 UPSread-writeAnyEventAny of counter overflow/underflow, setting UPG, or update through slave mode, generates an update interrupt or DMA request0CounterOnlyOnly counter overflow/underflow generates an update interrupt or DMA request1 UPDIS Update disable 1 1 UPDISread-writeEnabledUpdate event enabled0DisabledUpdate event disabled1 CEN Counter enable 0 1 CENread-writeDisabledCounter disabled0EnabledCounter enabled1 CTL1 CTL1 control register 1 0x04 0x10 read-write 0x0000 ISO3 Idle state of channel 3 output 14 1 ISO2N Idle state of channel 2 complementary output 13 1 ISO2 Idle state of channel 2 output 12 1 ISO1N Idle state of channel 1 complementary output 11 1 ISO1 Idle state of channel 1 output 10 1 ISO0N Idle state of channel 0 complementary output 9 1 ISO0Nread-writeLowCHn_ON=0 when POEN=00HighCHn_ON=1 when POEN=01 ISO0 Idle state of channel 0 output 8 1 ISO0read-writeLowCHn_O=0 (after a dead-time if CHn_ON is implemented) when POEN=00HighCHn_O=1 (after a dead-time if CHn_ON is implemented) when POEN=01 TI0S Channel 0 trigger input selection 7 1 TI0Sread-writeNormalThe CH0 pin input is selected as channel 0 trigger input0XORThe XOR of CH0, CH1 and CH2 pins are selected as channel 0 trigger input1 MMC Master mode control 4 3 MMCread-writeResetUse UPG bit from SWEVG register0EnableUse CEN bit from CTL0 register1UpdateUse the update event2CaptureComparePulseThe trigger output send a positive pulse when a capture or a compare match occurred in channel 03CompareO0CO0CPRE signal is used as trigger output4CompareO1CO1CPRE signal is used as trigger output5CompareO2CO2CPRE signal is used as trigger output6CompareO3CO3CPRE signal is used as trigger output7 DMAS DMA request source selection 3 1 DMASread-writeOnCompareCCx DMA request sent when CCx event occurs0OnUpdateCCx DMA request sent when update event occurs1 CCUC Commutation control shadow register update control 2 1 CCUCread-writeDefaultCapture/compare are updated only by setting the CMTG bit0WithRisingEdgeCapture/compare are updated by setting the CMTG bit or when an rising edge occurs on TRGI1 CCSE Commutation control shadow register enable 0 1 CCSEread-writeNotPreloadedThe shadow registers for CHxEN, CHxNEN and CHxCOMCTL bits are disabled0PreloadedThe shadow registers for CHxEN, CHxNEN and CHxCOMCTL bits are enabled1 SMCFG SMCFG slave mode configuration register 0x08 0x10 read-write 0x0000 ETP External trigger polarity 15 1 ETPread-writeNotInvertedETI is noninverted, active at high level or rising edge0InvertedETI is inverted, active at low level or falling edge1 SMC1 Part of SMC for enable External clock mode1 14 1 SMC1read-writeDisabledExternal clock mode 1 disabled0EnabledExternal clock mode 1 enabled. The counter is clocked by any active edge on the ETIF signal.1 ETPSC External trigger prescaler 12 2 ETPSCread-writeDiv1External trigger prescaler disabled0Div2ETI frequency divided by 21Div4ETI frequency divided by 42Div8ETI frequency divided by 83 ETFC External trigger filter control 8 4 ETFCread-writeNoFilterFilter disabled. fSAMP=fDTS, N=10TimerCk_N2fSAMP=fTIMER_CK, N=21TimerCk_N4fSAMP=fTIMER_CK, N=42TimerCk_N8fSAMP=fTIMER_CK, N=83FDTS_Div2_N6fSAMP=fDTS/2, N=64FDTS_Div2_N8fSAMP=fDTS/2, N=85FDTS_Div4_N6fSAMP=fDTS/4, N=66FDTS_Div4_N8fSAMP=fDTS/4, N=87FDTS_Div8_N6fSAMP=fDTS/8, N=68FDTS_Div8_N8fSAMP=fDTS/8, N=89FDTS_Div16_N5fSAMP=fDTS/16, N=510FDTS_Div16_N6fSAMP=fDTS/16, N=611FDTS_Div16_N8fSAMP=fDTS/16, N=812FDTS_Div32_N5fSAMP=fDTS/32, N=513FDTS_Div32_N6fSAMP=fDTS/32, N=614FDTS_Div32_N8fSAMP=fDTS/32, N=815 MSM Master/Slave mode 7 1 MSMread-writeNoSyncNo action0SyncThe effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event.1 TRGS Trigger selection 4 3 TRGSread-writeITI0Internal Trigger 0 (ITI0)0ITI1Internal Trigger 1 (ITI1)1ITI2Internal Trigger 2 (ITI2)2CI0F_EDCI0 Edge Detector (CI0F_ED)4CI0FE0Filtered Timer Input 0 (CI0FE0)5CI1FE1Filtered Timer Input 1 (CI1FE1)6ETIFPExternal Trigger input (ETIFP)7 OCRC OCPRE clear source selection 3 1 OCRCread-writeInputOCPRE_CLR_INT is connected to the OCPRE_CLR input0ETIFOCPRE_CLR_INT is connected to ETIF1 SMC Slave mode control 0 3 SMCread-writeDisabledSlave mode disabled - if CEN=1 then the prescaler is clocked directly by the internal clock.0QuadratureDecoderMode0Quadrature decoder mode 0 - Counter counts up/down on CI1FE1 edge depending on CI0FE0 level.1QuadratureDecoderMode1Quadrature decoder mode 1 - Counter counts up/down on CI0FE0 edge depending on CI1FE1 level.2QuadratureDecoderMode2Quadrature decoder mode 2 - Counter counts up/down on both CI0FE0 and CI1FE1 edges depending on the level of the other input.3RestartModeRestart Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers.4PauseModePause Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled.5EventModeEvent Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled.6ExternalClockModeExternal Clock Mode 0 - Rising edges of the selected trigger (TRGI) clock the counter.7 DMAINTEN DMAINTEN DMA/Interrupt enable register 0x0C 0x10 read-write 0x0000 TRGDEN Trigger DMA request enable 14 1 TRGDENread-writeDisabledTrigger DMA request disabled0EnabledTrigger DMA request enabled1 CMTDEN CMT DMA request enable 13 1 CMTDENread-writeDisabledCommutation DMA request disabled0EnabledCommutation DMA request enabled1 CH3DEN Channel 3 Capture/Compare DMA request enable 12 1 CH2DEN Channel 2 Capture/Compare DMA request enable 11 1 CH1DEN Channel 1 Capture/Compare DMA request enable 10 1 CH0DEN Channel 0 Capture/Compare DMA request enable 9 1 CH0DENread-writeDisabledCapture/compare DMA request disabled0EnabledCapture/compare DMA request enabled1 UPDEN Update DMA request enable 8 1 UPDENread-writeDisabledUpdate DMA request disabled0EnabledUpdate DMA request enabled1 BRKIE Break interrupt enable 7 1 BRKIEread-writeDisabledBreak interrupt disabled0EnabledBreak interrupt enabled1 TRGIE Trigger interrupt enable 6 1 TRGIEread-writeDisabledTrigger interrupt disabled0EnabledTrigger interrupt enabled1 CMTIE CMT interrupt enable 5 1 CMTIEread-writeDisabledCommutation interrupt disabled0EnabledCommutation interrupt enabled1 CH3IE Channel 3 Capture/Compare interrupt enable 4 1 CH2IE Channel 2 Capture/Compare interrupt enable 3 1 CH1IE Channel 1 Capture/Compare interrupt enable 2 1 CH0IE Channel 0 Capture/Compare interrupt enable 1 1 CH0IEread-writeDisabledCapture/compare interrupt disabled0EnabledCapture/compare interrupt enabled1 UPIE Update interrupt enable 0 1 UPIEread-writeDisabledUpdate interrupt disabled0EnabledUpdate interrupt enabled1 INTF INTF status register 0x10 0x10 read-write 0x0000 CH3OF Channel 3 Capture overflow flag 12 1 CH2OF Channel 2 Capture overflow flag 11 1 CH1OF Channel 2 Capture overflow flag 10 1 CH0OF Channel 0 Capture overflow flag 9 1 CH0OFread-writeClearNo over capture occurred0OverCaptureA capture event occured while CHnIF was already set1 BRKIF Break interrupt flag 7 1 BRKIFread-writeClearNo active level break detected0BreakActive level detected1 TRGIF Trigger interrupt flag 6 1 TRGIFread-writeClearNo trigger event occured0TriggeredTrigger event occurred1 CMTIF Channel commutation interrupt flag 5 1 CMTIFread-writeClearNo channel commutation event occured0CommutationChannel commutation event occurred1 CH3IF Channel 3 Capture/Compare interrupt enable 4 1 CH2IF Channel 2 Capture/Compare interrupt enable 3 1 CH1IF Channel 1s Capture/Compare interrupt enable 2 1 CH0IF Channel 0s Capture/Compare interrupt flag 1 1 CH0IFread-writeClearNo capture or compare interrupt occurred0CaptureCompareA capture or compare event occurred1 UPIF Update interrupt flag 0 1 UPIFread-writeClearNo update interrupt occurred0UpdatePendingUpdate interrupt pending.1 SWEVG SWEVG Software event generation register 0x14 0x10 write-only 0x0000 BRKG Break event generation 7 1 BRKGread-writeBreakGenerate a break event1 TRGG Trigger event generation 6 1 TRGGread-writeTriggerGenerate a trigger event1 CMTG Channel commutation event generation 5 1 CMTGread-writeUpdateGenerate a channel commutation event, updating capture/compare control registers based on the value of CCSE1 CH3G Channel 3 capture or compare event generation 4 1 CH2G Channel 2 capture or compare event generation 3 1 CH1G Channel 1 capture or compare event generation 2 1 CH0G Channel 0 capture or compare event generation 1 1 CH0Gread-writeCaptureCompareGenerate a capture or compare event1 UPG Update generation 0 1 UPGread-writeUpdateRe-initializes the timer counter and generates an update of the registers.1 CHCTL0_Output CHCTL0_Output Channel control register 0 (output mode) 0x18 0x10 read-write 0x0000 CH1COMCEN Channel 1 output compare clear enable 15 1 CH1COMCTL Channel 1 output compare mode 12 3 CH1COMSEN Channel 1 output compare shadow enable 11 1 CH1COMFEN Channel 1 output compare fast enable 10 1 CH1MS Channel 1 mode selection 8 2 CH0COMCEN Channel 0 output compare clear enable 7 1 CH0COMCENread-writeDisabledOutput compare clear disabled0EnabledOutput compare clear enabled1 CH0COMCTL Channel 0 compare output control 4 3 CH0COMCTLread-writeFrozenThe comparison between the output compare register CHyCV and the counter CNT has no effect on the outputs0ActiveOnMatchSet channel to active level on match. OxCPRE signal is forced high when the counter matches the capture/compare register CHyCV1InactiveOnMatchSet channel to inactive level on match. OxCPRE signal is forced low when the counter matches the capture/compare register CHyCV2ToggleOxCPRE toggles when CNT=CHyCV3ForceInactiveOxCPRE is forced low4ForceActiveOxCPRE is forced high5PwmMode0In upcounting, channel is active as long as CNT<CHyCV else inactive. In downcounting, channel is inactive as long as CNT>CHyCV else active6PwmMode1Inversely to PwmMode07 CH0COMSEN Channel 0 output compare shadow enable 3 1 CH0COMSENread-writeDisabledPreload register on CHyCV disabled. New values written to CHyCV are taken into account immediately0EnabledPreload register on CHyCV enabled. Preload value is loaded into active register on each update event1 CH0COMFEN Channel 0 output compare fast enable 2 1 CH0COMFENread-writeSlowThe minimum delay from an edge is 5 clock cycles0FastThe minimum delay from an edge is 3 clock cycles1 CH0MS Channel 0 I/O mode selection 0 2 CH0MSread-writeOutputChannel is configured as output0CI0Channel is configured as input, ISx is connected to CI0FE01CI1Channel is configured as input, ISx is connected to CI1FE02ITSChannel is configured as input, ISx is connected to ITS3 CHCTL0_Input CHCTL0_Input Channel control register 0 (input mode) CHCTL0_Output 0x18 0x10 read-write 0x0000 CH1CAPFLT Channel 1 input capture filter control 12 4 CH1CAPPSC Channel 1 input capture prescaler 10 2 CH1MS Channel 1 mode selection 8 2 CH0CAPFLT Channel 0 input capture filter control 4 4 CH0CAPFLTread-writeNoFilterFilter disabled. fSAMP=fDTS, N=10TimerCk_N2fSAMP=fTIMER_CK, N=21TimerCk_N4fSAMP=fTIMER_CK, N=42TimerCk_N8fSAMP=fTIMER_CK, N=83FDTS_Div2_N6fSAMP=fDTS/2, N=64FDTS_Div2_N8fSAMP=fDTS/2, N=85FDTS_Div4_N6fSAMP=fDTS/4, N=66FDTS_Div4_N8fSAMP=fDTS/4, N=87FDTS_Div8_N6fSAMP=fDTS/8, N=68FDTS_Div8_N8fSAMP=fDTS/8, N=89FDTS_Div16_N5fSAMP=fDTS/16, N=510FDTS_Div16_N6fSAMP=fDTS/16, N=611FDTS_Div16_N8fSAMP=fDTS/16, N=812FDTS_Div32_N5fSAMP=fDTS/32, N=513FDTS_Div32_N6fSAMP=fDTS/32, N=614FDTS_Div32_N8fSAMP=fDTS/32, N=815 CH0CAPPSC Channel 0 input capture prescaler 2 2 CH0CAPPSCread-writeDiv1Prescaler disabled, capture on every edge0Div2Capture every 2 edges1Div4Capture every 4 edges2Div8Capture every 8 edges3 CH0MS Channel 0 mode selection 0 2 CH0MSread-writeOutputChannel is configured as output0CI0Channel is configured as input, ISx is connected to CI0FEx1CI1Channel is configured as input, ISx is connected to CI1FEx2ITSChannel is configured as input, ISx is connected to ITS3 CHCTL1_Output CHCTL1_Output Channel control register 1 (output mode) 0x1C 0x10 read-write 0x0000 CH3COMCEN Channel 3 output compare clear enable 15 1 CH3COMCTL Channel 3 compare output control 12 3 CH3COMSEN Channel 3 output compare shadow enable 11 1 CH3COMFEN Channel 3 output compare fast enable 10 1 CH3MS Channel 3 mode selection 8 2 CH2COMCEN Channel 2 output compare clear enable 7 1 CH2COMCTL Channel 2 compare output control 4 3 CH2COMSEN Channel 2 output compare shadow enable 3 1 CH2COMFEN Channel 2 output compare fast enable 2 1 CH2MS Channel 2 mode selection 0 2 CHCTL1_Input CHCTL1_Input Channel control register 1 (input mode) CHCTL1_Output 0x1C 0x10 read-write 0x0000 CH3CAPFLT Channel 3 input capture filter control 12 4 CH3CAPPSC Channel 3 input capture prescaler 10 2 CH3MS Channel 3 mode selection 8 2 CH2CAPFLT Channel 2 input capture filter control 4 4 CH2CAPPSC Channel 2 input capture prescaler 2 2 CH2MS Channel 2 mode selection 0 2 CHCTL2 CHCTL2 Channel control register 2 0x20 0x10 read-write 0x0000 CH3P Channel 3 polarity 13 1 CH3EN Channel 3 enable 12 1 CH2NP Channel 2 complementary output polarity 11 1 CH2NEN Channel 2 complementary output enable 10 1 CH2P Channel 2 polarity 9 1 CH2EN Channel 2 enable 8 1 CH1NP Channel 1 complementary output polarity 7 1 CH1NEN Channel 1 complementary output enable 6 1 CH1P Channel 1 polarity 5 1 CH1EN Channel 1 enable 4 1 CH0NP Channel 0 complementary output polarity 3 1 CH0NEN Channel 0 complementary output enable 2 1 CH0P Channel 0 polarity 1 1 CH0Pread-writeNotInvertedActive high0InvertedActive low1 CH0EN Channel 0 enable 0 1 CH0ENread-writeDisabledChannel output is disabled0EnabledChannel output is enabled1 CNT CNT Counter register 0x24 0x10 read-write 0x0000 CNT current counter value 0 16 065535 PSC PSC Prescaler register 0x28 0x10 read-write 0x0000 PSC Prescaler value of the counter clock 0 16 065535 CAR CAR auto-reload register 0x2C 0x10 read-write 0x0000 CAR Counter auto reload value 0 16 065535 CREP CREP repetition counter register 0x30 0x10 read-write 0x0000 CREP Counter repetition value 0 8 0255 CH0CV CH0CV Channel 0 capture/compare value register 0x34 0x10 read-write 0x0000 CH0VAL Capture or compare value of channel 0 0 16 065535 CH1CV CH1CV Channel 1 capture/compare value register 0x38 0x10 read-write 0x0000 CH1VAL Capture or compare value of channel 1 0 16 065535 CH2CV CH2CV Channel 2 capture/compare value register 0x3C 0x10 read-write 0x0000 CH2VAL Capture or compare value of channel 2 0 16 065535 CH3CV CH3CV Channel 3 capture/compare value register 0x40 0x10 read-write 0x0000 CH3VAL Capture or compare value of channel 3 0 16 065535 CCHP CCHP channel complementary protection register 0x44 0x10 read-write 0x0000 POEN Primary output enable 15 1 POENread-writeDisabledChannel outputs are disabled0EnabledChannel outputs are enabled1 OAEN Output automatic enable 14 1 OAENread-writeManualPOEN cannot be set by hardware0AutomaticPOEN can be set by hardware automatically at the next update event1 BRKP Break polarity 13 1 BRKPread-writeInvertedBRKIN is active low0NotInvertedBRKIN is active high1 BRKEN Break enable 12 1 BRKENread-writeDisabledBreak inputs disabled0EnabledBreak inputs enabled1 ROS Run mode off-state configure 11 1 ROSread-writeDisabledWhen POEN is set, the channel output signals are disabled0EnabledWhen POEN is set, the channel output signals are enabled1 IOS Idle mode off-state configure 10 1 IOSread-writeDisabledWhen POEN is reset, the channel output signals are disabled0EnabledWhen POEN is reset, the channel output signals are enabled1 PROT Complementary register protect control 8 2 PROTread-writeDisabledWrite protection disabled0Mode0Protection mode 01Mode1Protection mode 12Mode2Protection mode 23 DTCFG Dead time configure 0 8 0255 DMACFG DMACFG DMA configuration register 0x48 0x10 read-write 0x0000 DMATC DMA transfer count 8 5 031 DMATA DMA transfer access start address 0 5 031 DMATB DMATB DMA Transfer buffer register 0x4C 0x10 read-write 0x0000 DMATB DMA transfer 0 16 065535 TIMER1 General-purpose-timers TIMER 0x40000000 0x0 0x400 registers TIMER1 15 CTL0 CTL0 control register 0 0x0 0x10 read-write 0x0000 CKDIV Clock division 8 2 ARSE Auto-reload shadow enable 7 1 CAM Counter aligns mode selection 5 2 DIR Direction 4 1 SPM Single pulse mode 3 1 SPMread-writeDisabledCounter is not stopped at update event0EnabledCounter stops counting at the next update event (clearing the CEN bit)1 UPS Update request source 2 1 UPDIS Update disable 1 1 CEN Counter enable 0 1 CTL1 CTL1 control register 1 0x04 0x10 read-write 0x0000 TI0S Channel 0 trigger input selection 7 1 TI0Sread-writeNormalThe CH0 pin input is selected as channel 0 trigger input0XORThe XOR of CH0, CH1 and CH2 pins are selected as channel 0 trigger input1 MMC Master mode control 4 3 MMCread-writeResetUse UPG bit from SWEVG register0EnableUse CEN bit from CTL0 register1UpdateUse the update event2 DMAS DMA request source selection 3 1 DMASread-writeOnCompareCCx DMA request sent when CCx event occurs0OnUpdateCCx DMA request sent when update event occurs1 SMCFG SMCFG Slave mode configuration register 0x08 0x10 read-write 0x0000 ETP External trigger polarity 15 1 ETPread-writeNotInvertedETI is noninverted, active at high level or rising edge0InvertedETI is inverted, active at low level or falling edge1 SMC1 Part of SMC for enable External clock mode1 14 1 SMC1read-writeDisabledExternal clock mode 1 disabled0EnabledExternal clock mode 1 enabled. The counter is clocked by any active edge on the ETIF signal.1 ETPSC External trigger prescaler 12 2 ETPSCread-writeDiv1External trigger prescaler disabled0Div2ETI frequency divided by 21Div4ETI frequency divided by 42Div8ETI frequency divided by 83 ETFC External trigger filter control 8 4 ETFCread-writeNoFilterFilter disabled. fSAMP=fDTS, N=10TimerCk_N2fSAMP=fTIMER_CK, N=21TimerCk_N4fSAMP=fTIMER_CK, N=42TimerCk_N8fSAMP=fTIMER_CK, N=83FDTS_Div2_N6fSAMP=fDTS/2, N=64FDTS_Div2_N8fSAMP=fDTS/2, N=85FDTS_Div4_N6fSAMP=fDTS/4, N=66FDTS_Div4_N8fSAMP=fDTS/4, N=87FDTS_Div8_N6fSAMP=fDTS/8, N=68FDTS_Div8_N8fSAMP=fDTS/8, N=89FDTS_Div16_N5fSAMP=fDTS/16, N=510FDTS_Div16_N6fSAMP=fDTS/16, N=611FDTS_Div16_N8fSAMP=fDTS/16, N=812FDTS_Div32_N5fSAMP=fDTS/32, N=513FDTS_Div32_N6fSAMP=fDTS/32, N=614FDTS_Div32_N8fSAMP=fDTS/32, N=815 MSM Master/Slave mode 7 1 MSMread-writeNoSyncNo action0SyncThe effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event.1 TRGS Trigger selection 4 3 TRGSread-writeITI0Internal Trigger 0 (ITI0)0ITI1Internal Trigger 1 (ITI1)1ITI2Internal Trigger 2 (ITI2)2CI0F_EDCI0 Edge Detector (CI0F_ED)4CI0FE0Filtered Timer Input 0 (CI0FE0)5CI1FE1Filtered Timer Input 1 (CI1FE1)6ETIFPExternal Trigger input (ETIFP)7 OCRC OCREF clear source selection 3 1 OCRCread-writeInputOCPRE_CLR_INT is connected to the OCPRE_CLR input0ETIFOCPRE_CLR_INT is connected to ETIF1 SMC Slave mode control 0 3 SMCread-writeDisabledSlave mode disabled - if CEN=1 then the prescaler is clocked directly by the internal clock.0QuadratureDecoderMode0Quadrature decoder mode 0 - Counter counts up/down on CI1FE1 edge depending on CI0FE0 level.1QuadratureDecoderMode1Quadrature decoder mode 1 - Counter counts up/down on CI0FE0 edge depending on CI1FE1 level.2QuadratureDecoderMode2Quadrature decoder mode 2 - Counter counts up/down on both CI0FE0 and CI1FE1 edges depending on the level of the other input.3RestartModeRestart Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers.4PauseModePause Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled.5EventModeEvent Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled.6ExternalClockModeExternal Clock Mode 0 - Rising edges of the selected trigger (TRGI) clock the counter.7 DMAINTEN DMAINTEN DMA and interrupt enable register 0x0C 0x10 read-write 0x0000 TRGDEN Trigger DMA request enable 14 1 TRGDENread-writeDisabledTrigger DMA request disabled0EnabledTrigger DMA request enabled1 CH3DEN Channel 3 Capture/Compare DMA request enable 12 1 CH2DEN Channel 2 Capture/Compare DMA request enable 11 1 CH1DEN Channel 1 Capture/Compare DMA request enable 10 1 CH0DEN Channel 0 Capture/Compare DMA request enable 9 1 CH0DENread-writeDisabledCapture/compare DMA request disabled0EnabledCapture/compare DMA request enabled1 UPDEN Update DMA request enable 8 1 UPDENread-writeDisabledUpdate DMA request disabled0EnabledUpdate DMA request enabled1 TRGIE Trigger interrupt enable 6 1 TRGIEread-writeDisabledTrigger interrupt disabled0EnabledTrigger interrupt enabled1 CH3IE Channel 3 Capture/Compare interrupt enable 4 1 CH2IE Channel 2 Capture/Compare interrupt enable 3 1 CH1IE Channel 1 Capture/Compare interrupt enable 2 1 CH0IE Channel 0 Capture/Compare interrupt enable 1 1 UPIE Update Capture/Compare interrupt enable 0 1 INTF INTF interrupt flag register 0x10 0x10 read-write 0x0000 CH3OF Channel 3 Capture overflow flag 12 1 CH2OF Channel 2 Capture overflow flag 11 1 CH1OF Channel 1 Capture overflow flag 10 1 CH0OF Channel 0 Capture overflow flag 9 1 TRGIF Trigger interrupt flag 6 1 TRGIFread-writeClearNo trigger event occured0TriggeredTrigger event occurred1 CH3IF Channel 3 Capture/Compare interrupt enable 4 1 CH2IF Channel 2 Capture/Compare interrupt enable 3 1 CH1IF Channel 1 Capture/Compare interrupt enable 2 1 CH0IF Channel 0 Capture/Compare interrupt flag 1 1 UPIF Update interrupt flag 0 1 SWEVG SWEVG event generation register 0x14 0x10 write-only 0x0000 TRGG Trigger generation 6 1 TRGGread-writeTriggerGenerate a trigger event1 CH3G Channel 3 capture or compare event generation 4 1 CH2G Channel 2 capture or compare event generation 3 1 CH1G Channel 1 capture or compare event generation 2 1 CH0G Channel 0 capture or compare event generation 1 1 UPG Update generation 0 1 CHCTL0_Output CHCTL0_Output Channel control register 0 (output mode) 0x18 0x10 read-write 0x0000 CH1COMCEN Channel 1 output compare clear enable 15 1 CH1COMCTL Channel 1 output compare mode 12 3 CH1COMSEN Channel 1 output compare shadow enable 11 1 CH1COMFEN Channel 1 output compare fast enable 10 1 CH1MS Channel 1 mode selection 8 2 CH0COMCEN Channel 0 output compare clear enable 7 1 CH0COMCTL Channel 0 compare output control 4 3 CH0COMSEN Channel 0 output compare shadow enable 3 1 CH0COMFEN Channel 0 output compare fast enable 2 1 CH0MS Channel 0 mode selection 0 2 CHCTL0_Input CHCTL0_Input Channel control register 0 (input mode) CHCTL0_Output 0x18 0x10 read-write 0x00000000 CH1CAPFLT Channel 1 input capture filter control 12 4 CH1CAPPSC Channel 1 input capture prescaler 10 2 CH1MS Channel 1 mode selection 8 2 CH0CAPFLT Channel 0 input capture filter control 4 4 CH0CAPPSC Channel 0 input capture prescaler 2 2 CH0MS Channel 0 mode selection 0 2 CHCTL1_Output CHCTL1_Output Channel control register 1 (output mode) 0x1C 0x10 read-write 0x0000 CH3COMCEN Channel 3 output compare clear enable 15 1 CH3COMCTL Channel 3 compare output control 12 3 CH3COMSEN Channel 3 compare output control 11 1 CH3COMFEN Channel 3 output compare fast enable 10 1 CH3MS Channel 3 mode selection 8 2 CH2COMCEN Channel 2 output compare clear enable 7 1 CH2COMCTL Channel 2 compare output control 4 3 CH2COMSEN Channel 2 output compare shadow enable 3 1 CH2COMFEN Channel 2 output compare fast enable 2 1 CH2MS Channel 2 mode selection 0 2 CHCTL1_Input CHCTL1_Input Channel control register 1 (input mode) CHCTL1_Output 0x1C 0x10 read-write 0x0000 CH3CAPFLT Channel 3 input capture filter control 12 4 CH3CAPPSC Channel 3 input capture prescaler 10 2 CH3MS Channel 3 mode selection 8 2 CH2CAPFLT Channel 2 input capture filter control 4 4 CH2CAPPSC Channel 2 input capture prescaler 2 2 CH2MS Channel 2 mode selection 0 2 CHCTL2 CHCTL2 Channel control register 2 0x20 0x10 read-write 0x0000 CH3NP Channel 3 complementary output polarity 15 1 CH3P Channel 3 polarity 13 1 CH3EN Channel 3 enable 12 1 CH2NP Channel 2 complementary output polarity 11 1 CH2P Channel 2 polarity 9 1 CH2EN Channel 2 enable 8 1 CH1NP Channel 1 complementary output polarity 7 1 CH1P Channel 1 polarity 5 1 CH1EN Channel 1 enable 4 1 CH0NP Channel 0 complementary output polarity 3 1 CH0P Channel 0 polarity 1 1 CH0EN Channel 0 enable 0 1 CNT CNT Counter register 0x24 0x20 read-write 0x00000000 CNT current counter value 0 32 04294967295 PSC PSC Prescaler register 0x28 0x10 read-write 0x0000 PSC Prescaler value of the counter clock 0 16 065535 CAR CAR Counter auto reload register 0x2C 0x20 read-write 0x0000 CAR Low Auto-reload value 0 32 04294967295 CH0CV CH0CV Channel 0 capture/compare value register 0x34 0x20 read-write 0x00000000 CH0VAL Capture or compare value of channel 0 0 32 04294967295 CH1CV CH1CV Channel 1 capture/compare value register 0x38 0x20 read-write 0x00000000 CH1VAL Capture or compare value of channel 1 0 32 04294967295 CH2CV CH2CV Channel 2 capture/compare value registerV 0x3C 0x20 read-write 0x00000000 CH2VAL Capture or compare value of channel 2 0 32 04294967295 CH3CV CH3CV Channel 3 capture/compare value register 0x40 0x20 read-write 0x00000000 CH3VAL Capture or compare value of channel 3 0 32 04294967295 DMACFG DMACFG DMA configuration register 0x48 0x10 read-write 0x0000 DMATC DMA transfer count 8 5 031 DMATA DMA transfer access start address 0 5 031 DMATB DMATB DMA Transfer buffer register 0x4C 0x20 read-write 0x0000 DMATB DMA transfer 0 16 065535 TIMER2 0x40000400 TIMER2 16 TIMER5 Basic-timers TIMER 0x40001000 0x0 0x400 registers TIMER5_DAC 17 CTL0 CTL0 control register 0 0x0 0x10 read-write 0x0000 ARSE Auto-reload shadow enable 7 1 SPM Single pulse mode 3 1 SPMread-writeDisabledCounter is not stopped at update event0EnabledCounter stops counting at the next update event (clearing the CEN bit)1 UPS Update source 2 1 UPDIS Update disable 1 1 CEN Counter enable 0 1 CTL1 CTL1 control register 1 0x04 0x10 read-write 0x0000 MMC Master mode control 4 3 MMCread-writeResetUse UPG bit from SWEVG register0EnableUse CEN bit from CTL0 register1UpdateUse the update event2 DMAINTEN DMAINTEN DMA/Interrupt enable register 0x0C 0x10 read-write 0x0000 UPDEN Update DMA request enable 8 1 UPDENread-writeDisabledUpdate DMA request disabled0EnabledUpdate DMA request enabled1 UPIE Update interrupt enable 0 1 INTF INTF status register 0x10 0x10 read-write 0x0000 UPIF Update interrupt flag 0 1 SWEVG SWEVG Software event generation register 0x14 0x10 write-only 0x0000 UPG Update generation 0 1 CNT CNT Counter register 0x24 0x10 read-write 0x00000000 CNT current counter value 0 16 065535 PSC PSC Prescaler register 0x28 0x10 read-write 0x0000 PSC Prescaler value of the counter clock 0 16 065535 CAR CAR Counter auto reload register 0x2C 0x10 read-write 0x00000000 CAR Counter auto reload value 0 16 065535 TIMER13 General-purpose-timers TIMER 0x40002000 0x0 0x400 registers TIMER13 19 CTL0 CTL0 control register 1 0x00 0x10 read-write 0x0000 CKDIV Clock division 8 2 ARSE Auto-reload shadow enable 7 1 UPS Update source 2 1 UPDIS Update disable 1 1 CEN Counter enable 0 1 DMAINTEN DMAINTEN Interrupt enable register 0x0C 0x10 read-write 0x0000 CH0IE Channel 0 interrupt enable 1 1 UPIE Update interrupt enable 0 1 INTF INTF interrupt flag register 0x10 0x10 read-write 0x0000 CH0OF Channel 0 Capture overflow flag 9 1 CH0IF Channel 0 interrupt flag 1 1 UPIF Update interrupt flag 0 1 SWEVG SWEVG Software event generation register 0x14 0x10 write-only 0x0000 CH0G Channel 0 capture or compare event generation 1 1 UPG Update generation 0 1 CHCTL0_Output CHCTL0_Output Channel control register 0 (output mode) 0x18 0x10 read-write 0x0000 CH0MS Channel 0 mode selection 0 2 CH0COMFEN Channel 0 output compare fast enable 2 1 CH0COMSEN Channel 0 output compare shadow enable 3 1 CH0COMCTL Channel 0 compare output control 4 3 CH0COMCEN Channel 0 output compare clear enable 7 1 CHCTL0_Input CHCTL0_Input Channel control register 0 (input mode) CHCTL0_Output 0x18 0x10 read-write 0x0000 CH0CAPFLT Channel 0 input capture filter control 4 4 CH0CAPPSC Channel 0 input capture prescaler 2 2 CH0MS Channel 0 mode selection 0 2 CHCTL2 CHCTL2 Channel control register 2 0x20 0x10 read-write 0x0000 CH0NP Channel 0 complementary output polarity 3 1 CH0P Channel 0 polarity 1 1 CH0EN Channel 0 enable 0 1 CNT CNT Counter register 0x24 0x10 read-write 0x0000 CNT current counter value 0 16 065535 PSC PSC Prescaler register 0x28 0x10 read-write 0x0000 PSC Prescaler value of the counter clock 0 16 065535 CAR CAR Counter auto reload register 0x2C 0x10 read-write 0x0000 CAR Counter auto reload register 0 16 065535 CH0CV CH0CV Channel 0 capture/compare value register 0x34 0x10 read-write 0x0000 CH0VAL Capture or compare value of channel 0 0 16 065535 IRMP IRMP Channel input remap register 0x50 0x10 read-write 0x0000 CI0_RMP Channel 0 input remap 0 2 CI0_RMPread-writeGPIOChannel 0 input is connected to GPIO0RTCCLKChannel 0 input is connected to RTCCLK1HXTAL_32Channel 0 input is connected to HXTAL / 322CKOUTSELChannel 0 input is connected to CKOUTSEL3 TIMER14 General-purpose-timers TIMER 0x40014000 0x0 0x400 registers TIMER14 20 CTL0 CTL0 control register 0 0x0 0x10 read-write 0x0000 CKDIV Clock division 8 2 ARSE Auto-reload shadow enable 7 1 SPM Single pulse mode 3 1 SPMread-writeDisabledCounter is not stopped at update event0EnabledCounter stops counting at the next update event (clearing the CEN bit)1 UPS Update source 2 1 UPDIS Update disable 1 1 CEN Counter enable 0 1 CTL1 CTL1 control register 1 0x4 0x10 read-write 0x0000 ISO1 Idle state of channel 1 output 10 1 ISO0N Idle state of channel 1 output 9 1 ISO0 Idle state of channel 0 output 8 1 MMC Master mode control 4 3 MMCread-writeResetUse UPG bit from SWEVG register0EnableUse CEN bit from CTL0 register1UpdateUse the update event2 DMAS DMA request source selection 3 1 DMASread-writeOnCompareCCx DMA request sent when CCx event occurs0OnUpdateCCx DMA request sent when update event occurs1 CCUC Commutation control shadow register update control 2 1 CCSE Commutation control shadow register enable 0 1 SMCFG SMCFG Slave mode configuration register 0x08 0x10 read-write 0x0000 MSM Master/Slave mode 7 1 MSMread-writeNoSyncNo action0SyncThe effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event.1 TRGS Trigger selection 4 3 TRGSread-writeITI0Internal Trigger 0 (ITI0)0ITI1Internal Trigger 1 (ITI1)1CI0F_EDCI0 Edge Detector (CI0F_ED)4CI0FE0Filtered Timer Input 0 (CI0FE0)5CI1FE1Filtered Timer Input 1 (CI1FE1)6 SMC Slave mode control 0 3 SMCread-writeDisabledSlave mode disabled - if CEN=1 then the prescaler is clocked directly by the internal clock.0RestartModeRestart Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers.4PauseModePause Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled.5EventModeEvent Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled.6ExternalClockModeExternal Clock Mode 0 - Rising edges of the selected trigger (TRGI) clock the counter.7 DMAINTEN DMAINTEN DMA and interrupt enable register 0x0C 0x10 read-write 0x0000 TRGDEN DMA and interrupt enable register 14 1 TRGDENread-writeDisabledTrigger DMA request disabled0EnabledTrigger DMA request enabled1 CH1DEN Channel 1 Capture/Compare DMA request enable 10 1 CH0DEN Channel 0 Capture/Compare DMA request enable 9 1 CH0DENread-writeDisabledCapture/compare DMA request disabled0EnabledCapture/compare DMA request enabled1 UPDEN Update DMA request enable 8 1 UPDENread-writeDisabledUpdate DMA request disabled0EnabledUpdate DMA request enabled1 BRKIE Break interrupt enable 7 1 TRGIE Trigger interrupt enable 6 1 TRGIEread-writeDisabledTrigger interrupt disabled0EnabledTrigger interrupt enabled1 CMTIE CMT interrupt enable 5 1 CH1IE Channel 1 Capture/Compare interrupt enable 2 1 CH0IE Channel 0 Capture/Compare interrupt enable 1 1 UPIE Update interrupt enable 0 1 INTF INTF interrupt flag register 0x10 0x10 read-write 0x0000 CH1OF Channel 1 Capture overflow flag 10 1 CH0OF Channel 0 Capture overflow flag 9 1 BRKIF Break interrupt flag 7 1 TRGIF Trigger interrupt flag 6 1 TRGIFread-writeClearNo trigger event occured0TriggeredTrigger event occurred1 CMTIF Channel commutation interrupt flag 5 1 CH1IF Channel 1 interrupt enable 2 1 CH0IF Channel 0 interrupt enable 1 1 UPIF Update interrupt flag 0 1 SWEVG SWEVG Software event generation register 0x14 0x10 write-only 0x0000 BRKG Break generation 7 1 TRGG Trigger generation 6 1 TRGGread-writeTriggerGenerate a trigger event1 CMTG Channel commutation event generation 5 1 CH1G Channel 1 capture or compare event generation 2 1 CH0G Channel 0 capture or compare event generation 1 1 UPG Update generation 0 1 CHCTL0_Output CHCTL0_Output Channel control register 0 (output mode) 0x18 0x10 read-write 0x00000000 CH1COMCEN Channel 1 output compare clear enable 15 1 CH1COMCTL Channel 1 output compare mode 12 3 CH1COMSEN Channel 1 output compare shadow enable 11 1 CH1COMFEN Channel 1 output compare fast enable 10 1 CH1MS Channel 1 mode selection 8 2 CH0COMCEN Channel 0 output compare clear enable 7 1 CH0COMCTL Channel 0 compare output control 4 3 CH0COMSEN Channel 0 output compare shadow enable 3 1 CH0COMFEN Channel 0 output compare fast enable 2 1 CH0MS Channel 0 mode selection 0 2 CHCTL0_Input CHCTL0_Input Channel control register 0 (input mode) CHCTL0_Output 0x18 0x10 read-write 0x00000000 CH1CAPFLT Channel 1 input capture filter control 12 4 CH1CAPPSC Channel 1 input capture prescaler 10 2 CH1MS Channel 1 mode selection 8 2 CH0CAPFLT Channel 0 input capture filter control 4 4 CH0CAPPSC Channel 0 input capture prescaler 2 2 CH0MS Channel 0 mode selection 0 2 CHCTL2 CHCTL2 Channel control register 2 0x20 0x10 read-write 0x0000 CH1NP Channel 1 complementary output polarity 7 1 CH1P Channel 1 polarity 5 1 CH1EN Channel 1 polarity 4 1 CH0NP Channel 0 complementary output polarity 3 1 CH0NEN Channel 0 complementary output enable 2 1 CH0P Channel 0 polarity 1 1 CH0EN Channel 0 enable 0 1 CNT CNT Channel 0 enable 0x24 0x10 read-write 0x0000 CNT current counter value 0 16 065535 PSC PSC Prescaler register 0x28 0x10 read-write 0x0000 PSC Prescaler value of the counter clock 0 16 065535 CAR CAR Counter auto reload register 0x2C 0x20 read-write 0x00000000 CAR Counter auto reload value 0 16 065535 CREP CREP Counter repetition register 0x30 0x10 read-write 0x0000 CREP Counter repetition value 0 8 0255 CH0CV CH0CV Channel 0 capture/compare value register 0x34 0x10 read-write 0x00000000 CH0VAL Capture or compare value of channel 0 0 16 065535 CH1CV CH1CV Channel 1 capture/compare value register 0x38 0x10 read-write 0x00000000 CH1VAL Capture or compare value of channel 1 0 16 065535 CCHP CCHP Complementary Channel Protection register 0x44 0x10 read-write 0x0000 POEN Primary output enable 15 1 OAEN Output automatic enable 14 1 BRKP Break polarity 13 1 BRKEN Break enable 12 1 ROS Run mode off-state configure 11 1 IOS Idle mode off-state configure 10 1 PROT Complementary register protect control 8 2 DTCFG Dead time configure 0 8 0255 DMACFG DMACFG DMA configuration register 0x48 0x10 read-write 0x0000 DMATC DMA transfer count 8 5 031 DMATA DMA transfer access start address 0 5 031 DMATB DMATB DMA transfer buffer register 0x4C 0x10 read-write 0x0000 DMATB DMA transfer 0 16 065535 TIMER15 General-purpose-timers TIMER 0x40014400 0x0 0x400 registers TIMER15 21 CTL0 CTL0 control register 0 0x0 0x10 read-write 0x0000 CKDIV Clock division 8 2 ARSE Auto-reload shadow enable 7 1 SPM Single pulse mode 3 1 SPMread-writeDisabledCounter is not stopped at update event0EnabledCounter stops counting at the next update event (clearing the CEN bit)1 UPS Update source 2 1 UPDIS Update disable 1 1 CEN Counter enable 0 1 CTL1 CTL1 control register 1 0x04 0x10 read-write 0x0000 ISO0N Idle state of channel 0 complementary output 9 1 ISO0 Idle state of channel 0 output 8 1 DMAS DMA request source selection 3 1 DMASread-writeOnCompareCCx DMA request sent when CCx event occurs0OnUpdateCCx DMA request sent when update event occurs1 CCUC Commutation control shadow register update control 2 1 CCSE Commutation control shadow register enable 0 1 DMAINTEN DMAINTEN DMA and interrupt enable register 0x0C 0x10 read-write 0x0000 CH0DEN Channel 0 Capture/Compare DMA request enable 9 1 CH0DENread-writeDisabledCapture/compare DMA request disabled0EnabledCapture/compare DMA request enabled1 UPDEN Update DMA request enable 8 1 UPDENread-writeDisabledUpdate DMA request disabled0EnabledUpdate DMA request enabled1 BRKIE Break interrupt enable 7 1 CMTIE CMT interrupt enable 5 1 CH0IE Channel 0 Capture/Compare interrupt enable 1 1 UPIE Update interrupt enable 0 1 INTF INTF interrupt flag register 0x10 0x10 read-write 0x0000 CH0OF Channel 0 Capture overflow flag 9 1 BRKIF Break interrupt flag 7 1 CMTIF Channel commutation interrupt flag 5 1 CH0IF Channel 0 interrupt flag 1 1 UPIF Update interrupt flag 0 1 SWEVG SWEVG Software event generation register 0x14 0x10 write-only 0x0000 BRKG Break event generation 7 1 CMTG Channel commutation event generation 5 1 CH0G Channel 0 capture or compare event generation 1 1 UPG Update generation 0 1 CHCTL0_Output CHCTL0_Output Channel control register 0 (output mode) 0x18 0x10 read-write 0x00000000 CH0COMCEN Channel 0 output compare clear enable 7 1 CH0COMCTL Channel 0 compare output control 4 3 CH0COMSEN Channel 0 output compare shadow enable 3 1 CH0COMFEN Channel 0 output compare fast enable 2 1 CH0MS Channel 0 mode selection 0 2 CHCTL0_Input CHCTL0_Input Channel control register 0 (input mode) CHCTL0_Output 0x18 0x10 read-write 0x0000 CH0CAPFLT Channel 0 input capture filter control 4 4 CH0CAPPSC Channel 0 input capture prescaler 2 2 CH0MS Channel 0 mode selection 0 2 CHCTL2 CHCTL2 Channel control register 2 0x20 0x10 read-write 0x0000 CH0NP Channel 0 complementary output polarity 3 1 CH0NEN Channel 0 complementary output enable 2 1 CH0P Channel 0 polarity 1 1 CH0EN Channel 0 enable 0 1 CNT CNT counter 0x24 0x10 read-write 0x0000 CNT current counter value 0 16 065535 PSC PSC Prescaler register 0x28 0x10 read-write 0x0000 PSC Prescaler value of the counter clock 0 16 065535 CAR CAR Counter auto reload register 0x2C 0x10 read-write 0x00000000 CAR Counter auto reload value 0 16 065535 CREP CREP Counter repetition register 0x30 0x10 read-write 0x0000 CREP Counter repetition value 0 8 0255 CH0CV CH0CV Channel 0 capture/compare value register 0x34 0x10 read-write 0x0000 CH0VAL Capture or compare value of channel 0 0 16 065535 CCHP CCHP Channel Complementary Protection register 0x44 0x10 read-write 0x0000 POEN Primary output enable 15 1 OAEN Output automatic enable 14 1 BRKP Break polarity 13 1 BRKEN Break enable 12 1 ROS Run mode off-state configure 11 1 IOS Idle mode off-state configure 10 1 PROT Complementary register protect control 8 2 DTCFG Dead time configure 0 8 0255 DMACFG DMACFG DMA configuration register 0x48 0x10 read-write 0x0000 DMATC DMA transfer count 8 5 031 DMATA DMA transfer access start address 0 5 031 DMATB DMATB DMA transfer buffer register 0x4C 0x10 read-write 0x0000 DMATB DMA transfer 0 16 065535 TIMER16 0x40014800 TIMER16 22 TSI Touch sensing Interface TSI 0x40024000 0x0 0x400 registers TSI 8 CTL CTL control register 0x0 0x20 read-write 0x00000000 CDT Charge State Duration Time 28 4 CTDT Charge Transfer State Duration Time 24 4 ECDT Extend Charge State Maximum Duration Time 17 7 ECEN Extend Charge State Enable 16 1 ECDIV ECCLK clock division factor 15 1 CTCDIV CTCLK clock division factor 12 3 MCN Max cycle number of a sequence 5 3 PINMOD Pin mode 4 1 EGSEL Edge selection 3 1 TRGMOD Trigger mode selection 2 1 TSIS TSI start 1 1 TSIEN TSI enable 0 1 INTEN INTEN interrupt enable register 0x4 0x20 read-write 0x00000000 MNERRIE Max Cycle Number Error Interrupt Enable 1 1 CTCFIE Charge-transfer complete flag Interrupt Enable 0 1 INTC INTC interrupt flag clear register 0x8 0x20 read-write 0x00000000 CMNERR Clear max cycle number error 1 1 CCTCF Clear charge-transfer complete flag 0 1 INTF INTF interrupt flag register 0xC 0x20 read-write 0x00000000 MNERR Max count error flag 1 1 CTCF Charge-Transfer complete flag 0 1 PHM PHM Pin hysteresis mode register 0x10 0x20 read-write 0x00000000 G5P3 G5P3 Schmitt trigger hysteresis mode 23 1 G5P2 G5P2 Schmitt trigger hysteresis mode 22 1 G5P1 G5P1 Schmitt trigger hysteresis mode 21 1 G5P0 G5P0 Schmitt trigger hysteresis mode 20 1 G4P3 G4P3 Schmitt trigger hysteresis mode 19 1 G4P2 G4P2 Schmitt trigger hysteresis mode 18 1 G4P1 G4P1 Schmitt trigger hysteresis mode 17 1 G4P0 G4P0 Schmitt trigger hysteresis mode 16 1 G3P3 G3P3 Schmitt trigger hysteresis mode 15 1 G3P2 G3P2 Schmitt trigger hysteresis mode 14 1 G3P1 G3P1 Schmitt trigger hysteresis mode 13 1 G3P0 G3P0 Schmitt trigger hysteresis mode 12 1 G2P3 G2P3 Schmitt trigger hysteresis mode 11 1 G2P2 G2P2 Schmitt trigger hysteresis mode 10 1 G2P1 G2P1 Schmitt trigger hysteresis mode 9 1 G2P0 G2P0 Schmitt trigger hysteresis mode 8 1 G1P3 G1P3 Schmitt trigger hysteresis mode 7 1 G1P2 G1P2 Schmitt trigger hysteresis mode 6 1 G1P1 G1P1 Schmitt trigger hysteresis mode 5 1 G1P0 G1P0 Schmitt trigger hysteresis mode 4 1 G0P3 G0P3 Schmitt trigger hysteresis mode 3 1 G0P2 G0P2 Schmitt trigger hysteresis mode 2 1 G0P1 G0P1 Schmitt trigger hysteresis mode 1 1 G0P0 G0P0 Schmitt trigger hysteresis mode 0 1 ASW ASW I/O analog switch register 0x18 0x20 read-write 0x00000000 G5P3 G5P3 analog switch enable 23 1 G5P2 G5P2 analog switch enable 22 1 G5P1 G5P1 analog switch enable 21 1 G5P0 G5P0 analog switch enable 20 1 G4P3 G4P3 analog switch enable 19 1 G4P2 G4P2 analog switch enable 18 1 G4P1 G4P1 analog switch enable 17 1 G4P0 G4P0 analog switch enable 16 1 G3P3 G3P3 analog switch enable 15 1 G3P2 G3P2 analog switch enable 14 1 G3P1 G3P1 analog switch enable 13 1 G3P0 G3P0 analog switch enable 12 1 G2P3 G2P3 analog switch enable 11 1 G2P2 G2P2 analog switch enable 10 1 G2P1 G2P1 analog switch enable 9 1 G2P0 G2P0 analog switch enable 8 1 G1P3 G1P3 analog switch enable 7 1 G1P2 G1P2 analog switch enable 6 1 G1P1 G1P1 analog switch enable 5 1 G1P0 G1P0 analog switch enable 4 1 G0P3 G0P3 analog switch enable 3 1 G0P2 G0P2 analog switch enable 2 1 G0P1 G0P1 analog switch enable 1 1 G0P0 G0P0 analog switch enable 0 1 SAMPCFG SAMPCFG I/O sample configuration register 0x20 0x20 read-write 0x00000000 G5P3 G5P3 sampling mode 23 1 G5P2 G5P2 sampling mode 22 1 G5P1 G5P1 sampling mode 21 1 G5P0 G5P0 sampling mode 20 1 G4P3 G4P3 sampling mode 19 1 G4P2 G4P2 sampling mode 18 1 G4P1 G4P1 sampling mode 17 1 G4P0 G4P0 sampling mode 16 1 G3P3 G3P3 sampling mode 15 1 G3P2 G3P2 sampling mode 14 1 G3P1 G3P1 sampling mode 13 1 G3P0 G3P0 sampling mode 12 1 G2P3 G2P3 sampling mode 11 1 G2P2 G2P2 sampling mode 10 1 G2P1 G2P1 sampling mode 9 1 G2P0 G2P0 sampling mode 8 1 G1P3 G1P3 sampling mode 7 1 G1P2 G1P2 sampling mode 6 1 G1P1 G1P1 sampling mode 5 1 G1P0 G1P0 sampling mode 4 1 G0P3 G0P3 sampling mode 3 1 G0P2 G0P2 sampling mode 2 1 G0P1 G0P1 sampling mode 1 1 G0P0 G0P0 sampling mode 0 1 CHCFG CHCFG I/O channel configuration register 0x28 0x20 read-write 0x00000000 G5P3 G5P3 channel mode 23 1 G5P2 G5P2 channel mode 22 1 G5P1 G5P1 channel mode 21 1 G5P0 G5P0 channel mode 20 1 G4P3 G4P3 channel mode 19 1 G4P2 G4P2 channel mode 18 1 G4P1 G4P1 channel mode 17 1 G4P0 G4P0 channel mode 16 1 G3P3 G3P3 channel mode 15 1 G3P2 G3P2 channel mode 14 1 G3P1 G3P1 channel mode 13 1 G3P0 G3P0 channel mode 12 1 G2P3 G2P3 channel mode 11 1 G2P2 G2P2 channel mode 10 1 G2P1 G2P1 channel mode 9 1 G2P0 G2P0 channel mode 8 1 G1P3 G1P3 channel mode 7 1 G1P2 G1P2 channel mode 6 1 G1P1 G1P1 channel mode 5 1 G1P0 G1P0 channel mode 4 1 G0P3 G0P3 channel mode 3 1 G0P2 G0P2 channel mode 2 1 G0P1 G0P1 channel mode 1 1 G0P0 G0P0 channel mode 0 1 GCTL GCTL I/O group control register 0x30 0x20 0x00000000 GC5 Analog I/O group 5 status 21 1 read-only GC4 Analog I/O group 4 status 20 1 read-only GC3 Analog I/O group 3 status 19 1 read-only GC2 Analog I/O group 2 status 18 1 read-only GC1 Analog I/O group 1 status 17 1 read-only GC0 Analog I/O group 0 status 16 1 read-only GE5 Analog I/O group 5 enable 5 1 read-write GE4 Analog I/O group 4 enable 4 1 read-write GE3 Analog I/O group 3 enable 3 1 read-write GE2 Analog I/O group 2 enable 2 1 read-write GE1 Analog I/O group 1 enable 1 1 read-write GE0 Analog I/O group 0 enable 0 1 read-write G0CYCN G0CYCN I/O group x cycle number register 0x34 0x20 read-only 0x00000000 CYCN Cycle number 0 14 G1CYCN G1CYCN I/O group x cycle number register 0x38 0x20 read-only 0x00000000 CYCN Cycle number 0 14 G2CYCN G2CYCN I/O group x cycle number register 0x3C 0x20 read-only 0x00000000 CYCN Cycle number 0 14 G3CYCN G3CYCN I/O group x cycle number register 0x40 0x20 read-only 0x00000000 CYCN Cycle number 0 14 G4CYCN G4CYCN I/O group x cycle number register 0x44 0x20 read-only 0x00000000 CYCN Cycle number 0 14 G5CYCN G5CYCN I/O group x cycle number register 0x48 0x20 read-only 0x00000000 CYCN Cycle number 0 14 USART0 Universal synchronous asynchronous receiver transmitter USART 0x40013800 0x0 0x400 registers USART0 27 CTL0 CTL0 Control register 0 0x0 0x20 read-write 0x00000000 EBIE End of Block interrupt enable 27 1 EBIEread-writeDisabledEnd of block interrupt is disabled0EnabledEnd of block interrupt is enabled1 RTIE Receiver timeout interrupt enable 26 1 RTIEread-writeDisabledReceiver timeout interrupt is disabled0EnabledReceiver timeout interrupt is enabled1 DEA Driver Enable assertion time 21 5 031 DED Driver Enable deassertion time 16 5 031 OVSMOD Oversampling mode 15 1 OVSMODread-writeOversampling16Oversampling by 160Oversampling8Oversampling by 81 AMIE ADDR match interrupt enable 14 1 AMIEread-writeDisabledAddress match interrupt is disabled0EnabledAddress match interrupt is enabled1 MEN Mute mode enable 13 1 MENread-writeDisabledReceiver in active mode permanently0EnabledReceiver can switch between mute mode and active mode1 WL Word length 12 1 WLread-writeBit88 data bits0Bit99 data bits1 WM Wakeup method in mute mode 11 1 WMread-writeIdleIdle line0AddressAddress mask1 PCEN Parity control enable 10 1 PCENread-writeDisabledParity control disabled0EnabledParity control enabled1 PM Parity selection 9 1 PMread-writeEvenEven parity0OddOdd parity1 PERRIE Parity error interrupt enable 8 1 PERRIEread-writeDisabledParity error interrupt is disabled0EnabledInterrupt is generated whenever PERR=1 in the STAT register1 TBEIE Transmitter register empty interrupt enable 7 1 TBEIEread-writeDisabledTransmission register empty interrupt is disabled0EnabledInterrupt is generated whenever TBE=1 in the STAT register1 TCIE Transmission complete interrupt enable 6 1 TCIEread-writeDisabledTransmission complete interrupt is disabled0EnabledInterrupt is generated whenever TC=1 in the STAT register1 RBNEIE Read data buffer not empty interrupt and overrun error interrupt enable 5 1 RBNEIEread-writeDisabledRead data buffer not empty and overrrun error interrupts are disabled0EnabledInterrupt is generated whenever ORERR=1 or RBNE=1 in the STAT register1 IDLEIE IDLE line detected interrupt enable 4 1 IDLEIEread-writeDisabledIdle line detected interrupt is disabled0EnabledInterrupt is generated whenever IDLEF=1 in the STAT register1 TEN Transmitter enable 3 1 TENread-writeDisabledTransmitter is disabled0EnabledTransmitter is enabled1 REN Receiver enable 2 1 RENread-writeDisabledReceiver is disabled0EnabledReceiver is enabled1 UESM USART enable in Deep-sleep mode 1 1 UESMread-writeDisabledUSART not able to wake the MCU from deep-sleep mode0EnabledUSART is able to wake the MCU from deep-sleep mode, as long as the clock source for the USART is IRC8M or LXTAL1 UEN USART enable 0 1 UENread-writeDisabledUSART prescaler and outputs disabled0EnabledUSART prescaler and outputs is enabled1 CTL1 CTL1 Control register 1 0x4 0x20 read-write 0x00000000 ADDR Address of the USART terminal 24 8 0255 RTEN Receiver timeout enable 23 1 RTENread-writeDisabledReceiver timeout feature disabled0EnabledReceiver timeout feature enabled1 ABDM Auto baud rate mode 21 2 ABDMread-writeStartMeasurement of the start bit is used to detect the baud rate0EdgeFalling edge to falling edge measurement1 ABDEN Auto baud rate enable 20 1 ABDENread-writeDisabledAuto baud rate detection is disabled0EnabledAuto baud rate detection is enabled1 MSBF Most significant bit first 19 1 MSBFread-writeLSBData is transmitted/received with data bit 0 first, following the start bit0MSBData is transmitted/received with MSB (bit 7/8/9) first, following the start bit1 DINV Data bit level inversion 18 1 DINVread-writePositiveLogical data from the data register are send/received in positive/direct logic0NegativeLogical data from the data register are send/received in negative/inverse logic1 TINV TX pin level inversion 17 1 TINVread-writeStandardTX pin signal works using the standard logic levels0InvertedTX pin signal values are inverted1 RINV RX pin level inversion 16 1 RINVread-writeStandardRX pin signal works using the standard logic levels0InvertedRX pin signal values are inverted1 STRP Swap TX/RX pins 15 1 STRPread-writeStandardTX/RX pins are used as defined in standard pinout0SwappedThe TX and RX pins functions are swapped1 LMEN LIN mode enable 14 1 LMENread-writeDisabledLIN mode disabled0EnabledLIN mode enabled1 STB STOP bits length 12 2 STBread-writeStop11 stop bit0Stop0p50.5 stop bit1Stop22 stop bit2Stop1p51.5 stop bit3 CKEN CK pin enable 11 1 CKENread-writeDisabledCK pin disabled0EnabledCK pin enabled1 CPL Clock polarity 10 1 CPLread-writeNotInvertedSteady low value on CK pin outside tranmission window0InvertedSteady high value on CK pin outside tranmission window1 CPH Clock phase 9 1 CPHread-writeFirstThe first clock transition is the first data capture edge0SecondThe second clock transition is the first data capture edge1 CLEN CK length 8 1 CLENread-writeNotOutputThe clock pulse of the last data bit is not output to the CK pin0OutputThe clock pulse of the last data bit is output to the CK pin1 LBDIE LIN break detection interrupt enable 6 1 LBDIEread-writeDisabledInterrupt is disabled0EnabledAn interrupt is generated whenever LBDF=1 in the STAT register1 LBLEN LIN break frame length 5 1 LBLENread-writeBit1010-bit break detection0Bit1111-bit break detection1 ADDM Address detection mode 4 1 ADDMread-writeBit44-bit address detection0FullFull-bit address detection1 CTL2 CTL2 Control register 2 0x8 0x20 read-write 0x00000000 WUIE Wakeup from Deep-sleep mode interrupt enable 22 1 WUIEread-writeDisabledWake-up from deep-sleep mode interrupt is disabled0EnabledWake-up from deep-sleep mode interrupt is generated whenever WUF=1 in the STAT register1 WUM Wakeup mode from Deep-sleep mode 20 2 WUMread-writeAddressWUF active on address match0StartWUF active on start bit detection2RXNEWUF active on RBNE3 SCRTNUM Smartcard auto-retry number 17 3 07 DEP Driver enable polarity mode 15 1 DEPread-writeHighDE signal is active high0LowDE signal is active low1 DEM Driver enable mode 14 1 DEMread-writeDisabledDE function is disabled0EnabledThe DE signal is output on the RTS pin1 DDRE Disable DMA on reception error 13 1 DDREread-writeNotDisabledDMA is not disabled in case of reception error0DisabledDMA is disabled following a reception error1 OVRD Overrun Disable 12 1 OVRDread-writeEnabledOverrun Error Flag, ORE, is set when received data is not read before receiving new data0DisabledOverrun functionality is disabled. If new data is received while the RXNE flag is still set the ORE flag is not set and the new received data overwrites the previous content of the RDATA register1 OSB One sample bit method 11 1 OSBread-writeSample3Three sample bit method0Sample1One sample bit method1 CTSIE CTS interrupt enable 10 1 CTSIEread-writeDisabledInterrupt is disabled0EnabledAn interrupt is generated whenever CTS=1 in the STAT register1 CTSEN CTS enable 9 1 CTSENread-writeDisabledCTS hardware flow control disabled0EnabledCTS mode enabled, data is only transmitted when the CTS input is asserted1 RTSEN RTS enable 8 1 RTSENread-writeDisabledRTS hardware flow control disabled0EnabledRTS output enabled, data is only requested when there is space in the receive buffer1 DENT DMA enable transmitter 7 1 DENTread-writeDisabledDMA mode is disabled for transmission0EnabledDMA mode is enabled for transmission1 DENR DMA enable for reception 6 1 DENRread-writeDisabledDMA mode is disabled for reception0EnabledDMA mode is enabled for reception1 SCEN Smartcard mode enable 5 1 SCENread-writeDisabledSmartcard Mode disabled0EnabledSmartcard Mode enabled1 NKEN NKEN enable in Smartcard mode 4 1 NKENread-writeDisabledNACK transmission in case of parity error is disabled0EnabledNACK transmission during parity error is enabled1 HDEN Half-duplex selection 3 1 HDENread-writeNotSelectedHalf duplex mode is not selected0SelectedHalf duplex mode is selected1 IRLP IrDA low-power 2 1 IRLPread-writeNormalNormal mode0LowPowerLow-power mode1 IREN IrDA mode enable 1 1 IRENread-writeDisabledIrDA disabled0EnabledIrDA enabled1 ERRIE Error interrupt enable 0 1 ERRIEread-writeDisabledError interrupt is disabled0EnabledAn interrupt is generated when FERR=1 or ORERR=1 or NERR=1 in the STAT register1 BAUD BAUD Baud rate generator register 0x0C 0x20 read-write 0x00000000 INTDIV Integer part of baud-rate divider 4 12 04095 FRADIV Fraction part of baud-rate divider 0 4 015 GP GP Prescaler and guard time configuration register 0x10 0x20 read-write 0x00000000 GUAT Guard time value in smartcard mode 8 8 0255 PSC Prescaler value for dividing the system clock 0 8 0255 RT RT Receiver timeout register 0x14 0x20 read-write 0x00000000 BL Block Length 24 8 0255 RT Receiver timeout value 0 24 016777215 CMD CMD Request register 0x18 0x20 write-only 0x00000000 TXFCMD Transmit data flush request 4 1 TXFCMDread-writeDiscardSet the TBE flag. This allows to discard the transmit data1 RXFCMD Receive data flush command 3 1 RXFCMDread-writeDiscardClears the RBNE flag. This allows to discard the received data without reading it, and avoid an overrun condition1 MMCMD Mute mode command 2 1 MMCMDread-writeMutePuts the USART in mute mode and sets the RWU flag1 SBKCMD Send break command 1 1 SBKCMDread-writeBreakSets the SBKF flag and request to send a BREAK on the line, as soon as the transmit machine is available1 ABDCMD Auto baudrate detection command 0 1 ABDCMDread-writeRequestResets the ABRF flag in the USART_ISR and request an automatic baud rate measurement on the next received data frame1 STAT STAT Interrupt & status register 0x1C 0x20 read-only 0x000000C0 REA Receive enable acknowledge flag 22 1 TEA Transmit enable acknowledge flag 21 1 WUF Wakeup from Deep-sleep mode flag 20 1 RWU Receiver wakeup from Mute mode 19 1 SBF Send break flag 18 1 AMF ADDR match flag 17 1 BSY Busy flag 16 1 ABDF Auto baudrate detection flag 15 1 ABDE Auto baudrate detection error 14 1 EBF End of block flag 12 1 RTF Receiver timeout 11 1 CTS CTS level 10 1 CTSF CTS change flag 9 1 LBDF LIN break detection flag 8 1 TBE Transmit data register empty 7 1 TC Transmission complete 6 1 RBNE Read data buffer not empty 5 1 IDLEF IDLE line detected flag 4 1 ORERR Overrun error 3 1 NERR Noise error flag 2 1 FERR Frame error flag 1 1 PERR Parity error flag 0 1 INTC INTC Interrupt flag clear register 0x20 0x20 write-only 0x00000000 WUC Wakeup from Deep-sleep mode clear 20 1 WUCread-writeClearClears the WUF flag in the STAT register1 AMC ADDR match clear 17 1 AMCread-writeClearClears the AMF flag in the STAT register1 EBC End of timeout clear 12 1 EBCread-writeClearClears the EBF flag in the STAT register1 RTC Receiver timeout clear flag 11 1 RTCread-writeClearClears the RCF flag in the STAT register1 CTSC CTS change clear 9 1 CTSCread-writeClearClears the CTSF flag in the STAT register1 LBDC LIN break detected clear 8 1 LBDCread-writeClearClears the LBDF flag in the STAT register1 TCC Transmission complete clear flag 6 1 TCCread-writeClearClears the TC bit in the STAT register1 IDLEC Idle line detected clear 4 1 IDLECread-writeClearClears the IDLEF flag in the STAT register1 OREC Overrun error clear flag 3 1 ORECread-writeClearClears the ORERR bit in the STAT register1 NEC Noise detected clear 2 1 NECread-writeClearClears the NERR bit in the STAT register1 FEC Framing error clear flag 1 1 FECread-writeClearClears the FERR bit in the STAT register1 PEC Parity error clear flag 0 1 PECread-writeClearClears the PERR bit in the STAT register1 RDATA RDATA Receive data register 0x24 0x20 read-only 0x00000000 RDATA Receive data value 0 9 0511 TDATA TDATA Transmit data register 0x28 0x20 read-write 0x00000000 TDATA Transmit data value 0 9 0255 USART1 0x40004400 USART1 28 WWDGT Window watchdog timer WWDGT 0x40002C00 0x0 0x400 registers WWDGT 0 CTL CTL Control register 0x0 0x20 read-write 0x0000007F WDGTEN Start the Window watchdog timer 7 1 WDGTENread-writeDisabledWatchdog disabled0EnabledWatchdog enabled1 CNT watchdog timer counter 0 7 0127 CFG CFG Configuration register 0x04 0x20 read-write 0x0000007F EWIE Early wakeup interrupt enable 9 1 EWIEWwriteEnableinterrupt occurs whenever the counter reaches the value 0x401 PSC Prescaler 7 2 PSCread-writeDiv1Counter clock (PCLK1 div 4096) div 10Div2Counter clock (PCLK1 div 4096) div 21Div4Counter clock (PCLK1 div 4096) div 42Div8Counter clock (PCLK1 div 4096) div 83 WIN The Window value 0 7 0127 STAT STAT Status register 0x08 0x20 read-write 0x00000000 EWIF EEarly wakeup interrupt flag 0 1 EWIFRreadPendingThe EWI Interrupt Service Routine has been triggered1FinishedThe EWI Interrupt Service Routine has been serviced0 EWIFWwriteFinishedThe EWI Interrupt Service Routine has been serviced0